STEVAL-PCC012V1 STMicroelectronics, STEVAL-PCC012V1 Datasheet - Page 7

BOARD DEM CONN GATEWAY STM32F107

STEVAL-PCC012V1

Manufacturer Part Number
STEVAL-PCC012V1
Description
BOARD DEM CONN GATEWAY STM32F107
Manufacturer
STMicroelectronics
Series
STM32r
Type
Other Power Managementr
Datasheets

Specifications of STEVAL-PCC012V1

Main Purpose
Interface, Connectivity
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
STM32F107
Primary Attributes
Ethernet and 4 Digital/Analog Connectors
Secondary Attributes
On-Board LEDs and Joystick
Interface Type
Ethernet, USB, I2C, SPI, UART
Operating Supply Voltage
3.3 V
Product
Power Management Development Tools
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
STM32F107xx
Other names
497-10757

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STEVAL-PCC012V1
Manufacturer:
STMicroelectronics
Quantity:
1
STM32F105xx, STM32F107xx
List of figures
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Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 12
STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view. . . . . . . . 23
STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout . . . . . . . . . . . . . . 24
STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout . . . . . . . . . . . . . . . 25
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Typical current consumption on V
different V
Typical current consumption in Stop mode with regulator in Run mode
versus temperature at different V
Typical current consumption in Stop mode with regulator in Low-power
mode versus temperature at different V
Typical current consumption in Standby mode versus temperature at
different V
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SPI timing diagram - slave mode and CPHA = 1
SPI timing diagram - master mode
I
I
USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . 68
Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Power supply and reference decoupling (V
Power supply and reference decoupling (V
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 81
LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Recommended footprint
LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2
2
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
S slave timing diagram (Philips protocol)
S master timing diagram (Philips protocol)
BAT
DD
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Doc ID 15274 Rev 5
DD
BAT
(1)
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
with RTC on vs. temperature at
DD
(1)
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
REF+
REF+
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
(1)
not connected to V
connected to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DDA
DDA
). . . . . . . . . . . . . . . . . 75
). . . . . . . . . . . . . . 75
List of figures
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