STEVAL-PCC012V1 STMicroelectronics, STEVAL-PCC012V1 Datasheet - Page 50

BOARD DEM CONN GATEWAY STM32F107

STEVAL-PCC012V1

Manufacturer Part Number
STEVAL-PCC012V1
Description
BOARD DEM CONN GATEWAY STM32F107
Manufacturer
STMicroelectronics
Series
STM32r
Type
Other Power Managementr
Datasheets

Specifications of STEVAL-PCC012V1

Main Purpose
Interface, Connectivity
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
STM32F107
Primary Attributes
Ethernet and 4 Digital/Analog Connectors
Secondary Attributes
On-Board LEDs and Joystick
Interface Type
Ethernet, USB, I2C, SPI, UART
Operating Supply Voltage
3.3 V
Product
Power Management Development Tools
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
STM32F107xx
Other names
497-10757

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STEVAL-PCC012V1
Manufacturer:
STMicroelectronics
Quantity:
1
Electrical characteristics
5.3.8
50/101
All timings are derived from tests performed under ambient temperature and V
voltage conditions summarized in
Table 26.
1. The wakeup times are measured from the wakeup event to the point in which the user application code
PLL, PLL2 and PLL3 characteristics
The parameters given in
temperature and V
Table 27.
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
Table 28.
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
f
f
f
t
Jitter
f
f
f
t
Jitter
PLL_IN
PLL_OUT
VCO_OUT
LOCK
PLL_IN
PLL_OUT
VCO_OUT
LOCK
reads the first instruction.
the range defined by f
the range defined by f
Symbol
Symbol
t
t
t
WUSTDBY
WUSLEEP
WUSTOP
Symbol
(1)
(1)
(1)
Low-power mode wakeup timings
PLL characteristics
PLL2 and PLL3 characteristics
PLL input clock
Pulse width at high level
PLL multiplier output clock
PLL VCO output
PLL lock time
Cycle-to-cycle jitter
PLL input clock
Pulse width at high level
PLL multiplier output clock
PLL VCO output
PLL lock time
Cycle-to-cycle jitter
DD
Wakeup from Sleep mode
Wakeup from Stop mode (regulator in run mode)
Wakeup from Stop mode (regulator in low power mode)
Wakeup from Standby mode
PLL_OUT
PLL_OUT
supply voltage conditions summarized in
Table 27
.
.
(2)
(2)
Parameter
Doc ID 15274 Rev 5
Parameter
Table
and
Table 28
Parameter
9.
are derived from tests performed under
Min
Min
STM32F105xx, STM32F107xx
30
40
80
3
30
18
36
3
(1)
Table
(1)
9.
Max
Max
148
350
400
144
350
300
74
12
72
5
(1)
Typ
(1)
1.8
3.6
5.4
50
DD
supply
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
Unit
ns
µs
ps
ns
µs
ps
µs
µs
µs

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