XR88C681CP/40-F Exar Corporation, XR88C681CP/40-F Datasheet - Page 58

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XR88C681CP/40-F

Manufacturer Part Number
XR88C681CP/40-F
Description
IC UART CMOS DUAL 40PDIP
Manufacturer
Exar Corporation
Type
CMOS Dual Channel UARTr
Datasheet

Specifications of XR88C681CP/40-F

Number Of Channels
2, DUART
Package / Case
40-DIP (0.600", 15.24mm)
Features
*
Fifo's
1 Byte, 3 Byte
Voltage - Supply
5V
With Parallel Port
Yes
With Cmos
Yes
Mounting Type
Through Hole
Data Rate
1 Mbps
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Supply Current
15 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
Through Hole
Operating Supply Voltage
5 V
Propagation Delay Time Ns
400 ns
No. Of Channels
2
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
DIP
No. Of Pins
40
Filter Terminals
DIP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1328-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR88C681CP/40-F
Manufacturer:
Linear
Quantity:
185
Figure 30 shows that the phase relationship between the Receiver’s sampling point and each serial data bit is changing.
In this case, the Receiver is sampling each serial data bit, earlier and earlier in the bit period, with each successive data
bit. This phenomenon is known as receiver drift. If there is no correction for receiver drift, there will be many errors in the
transmission and reception of this serial data, as depicted in Figure 31.
Figure 31 shows the Receiver sampling an eight bit string of data with bit pattern 0101010. It is interesting to note that, in
Figure 31, the Receiver sampled 01010010. It should be noted that Receiver drift can also be a problem is the local
Receiver is slower than the remote Transmitter clock.
Received Data
Rev. 2.11
Actual Data
Figure 30. Receiver (1X) Sampling, if the RX Clock is Slightly Faster Than the TX Clock
0
0
Figure 31. Illustration of an Error due to Receiver Drift
1
1
0
0
1
58
1
0
0
0
1
1
0
0
1
1

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