xr88c681 Exar Corporation, xr88c681 Datasheet
xr88c681
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xr88c681 Summary of contents
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... The DUART is designed for use in microprocessor based systems and may be used in a polled or interrupt driven environment. The XR88C681 device offers a single IC solution for the 8080/85, 8086/88, Z80, Z8000, 68xx and 65xx microprocessor families. ORDERING INFORMATION Part No ...
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... Mode Registers Status Register Channel A Operation Control CRB CRA Data Bus Command Decoder Buffer Address Decoder -RD -WR -CS RESET Figure 1. Block Diagram of the XR88C681 Rev. 2.11 RXDB IP0 - IP6 RSR IPR Change of State Detectors RHR IPCR ACR Status Register Channel B Input Port ...
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... TXDB TXDA 8 21 OP1 OP0 GND -INTR Lead PDIP (0.600”) 3 XR88C681 IP3 IP4/IEI IP5/IEO 3 38 IP1 -IP6/IACK IP2 - IP0 RESET 7 34 -WR X2 ...
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PIN DESCRIPTION 44 PLCC 40 PDIP, 28 PDIP CDIP ...
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... The bus is tri-stated when the during an IACK cycle (in the Z-Mode). OP6 O Output 6 (General Purpose Output). This output pin can also be programmed to function as the open drain, active- (-TXRDY_A) low, “Transmitter Ready” indicator output for Channel A ( TXRDY_A XR88C681 CS input is “high”, except - ...
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... If the oscillator is not used, an external clock signal must be supplied at this input. In order for the XR88C681 device to function properly, the user must supply a signal with frequencies be- tween 2.0MHz and 4.0MHz. This requirement can be met by either a crystal oscillator or by the external TTL-compatible clock signal ...
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... If this active-high input logic “high”, the DUART is ca- pable of generating all non-masked Interrupt Requests to the CPU. If this input logic “low”, the DUART is inhibited from generating any Interrupt Requests to the CPU. V PWR Most Positive Power Supply XR88C681 ...
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DC ELECTRICAL CHARACTERISTICS Test Conditions 70° Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Input High Voltage (Military Input High Voltage (X1/CLK) IHX1 V Output Low Voltage ...
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... AC ELECTRICAL CHARACTERISTICS Test Conditions 70° Symbol Parameter Reset Timing (See Figure 51) t RESET Pulse Width RES XR88C681 Read and Write Cycle Timing (Figure 52) t A0-A3 Setup Time to RD Low t A0-A3 Hold Time from RD Low t CS Setup Time to RD, WR Low ...
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Symbol Parameter t X1/CLK (External) High or Low CLK Time t X1/CLK Crystal or External CLK Frequency Rev. 2.11 Min. Typ. Max. Unit 100 ns 7.372 MHz 10 Conditions ...
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... and IACK low, guaranteeing that they will be low for at least one CLK period Specifications are subject to change without notice 1 7V -65° 150° C -0.5V to +7V 11 XR88C681 Unit Conditions ns MHz ns MHz MHz and typical CC CSs. ...
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This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive stat- ic charge. Nonetheless suggested that conventional precautions be taken to avoid applying any voltage larger than the rated ...
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... SYSTEM DESCRIPTION The XR88C681 consists of two independent, full-duplex communication channels; each consisting of their own Transmitter and Receiver. Each channel of the DUART may be independently programmed for operating mode and data format. The DUART can interface to a wide range of processors with a minimal amount of components ...
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... And finally, the DUART also contains other registers that support functions other than serial data communication, such as the parallel ports and the counters/timers. D OPCR- Output Port Control Register D IPCR - Input Port Configuration Register D CTUR - Counter/Timer Upper Byte Register D CTLR - Counter/Timer Lower Byte Register Rev. 2.11 Processor to the XR88C681 Device 14 -WR -RD RESET ...
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... MR1A, MR2A SRA MISR RHRA IPCR ISR CTU CTL MR1B, MR2B SRB RHRB IVR IP SCC STC 15 XR88C681 Write Mode Registers Register Name Symbol Mode Register, MR1A, MR2A Channel A Clock Select Register, CSRA Channel A Command Register A CRA Tx Holding Register, THRA Channel A Auxiliary Control ...
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Command Register. Therefore, both Mode Registers, within a given channel, have the same logical address. The features and functions of the DUART that are controlled by the Mode Registers are discussed in detail in ...
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... Set Tx BRG Select Extend Bit. Sets the channel’s “Transmitter BRG Select Extend Bit” Clear Tx BRG Select Extend Bit. Clears the chan- nel’s “Transmitter BRG Select Extend Bit” Unless Otherwise Specified (Cont’d) 17 XR88C681 ...
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Bit 7 Bit Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, In addition to the commands which are available through the command registers, the DUART also offers “Address-Triggered” commands. ...
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... Condition, the user must do two things: 1. Write the appropriate data to the lower nibble of the Auxiliary Control Register, ACR[3:0]. In this step, the user is specifying which Input Pins should trigger an “Input Port Change” Interrupt request. 19 XR88C681 Table 4 lists these Address Location (in DUART Address Space) 05 (Read Only) ...
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Write a logic “1” to IMR[7]. ISR[6] Delta Break Indicator - Channel B When this bit is set, it indicates that the Channel B receiver has detected the beginning or end of a received break (RB). This bit is ...
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... THR and RHR (FIFO) conditions; the Counter/Timer Ready condition, and to changes in the Break Condition (at the Receiver). However, aside from the “Delta Break Condition” (RB), the DUART’s Interrupt Structure does not allow for interrupt requests due to 21 XR88C681 Bit 2 Bit 1 Bit 0 Delta Break RXRDY/ ...
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... Error Mode to “Character” (MR1n[5] = 0). C.6 Servicing DUART Interrupts Interrupt servicing with the XR88C681 DUART falls into two broad categories: I-Mode and Z-Mode. I-Mode has historically been referred to as the “Intel” Mode. Likewise, the Z-Mode has been referred to as the “ ...
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... Request input; The Z-80 CPU uses the exact same approach as presented for the 8080A CPU. Direct Interrupt The Z-80 will branch to 0038H in system memory if the interrupt request pin is asserted. 23 XR88C681 Table 7 also presents the type of interrupt Comments INTA, which can be used to “gate” - IRQ. - ...
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C.6.1.1 8051 Microcontroller The 8051 family of microcontrollers is manufactured by Intel and comes with a variety of amenities. Some of these amenities include chip serial port D Four 8 bit I/O port (P0 - P3) D Two ...
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... Port 1 pins; thus they are used solely for interfacing to external devices. 8032/8052 ICs, which use P1.0 and P1.1 either as I/O lines or as external inputs to the third timer. address bus for designs with external code memory of more than 256 bytes of external data memory (A8 - A15). 25 XR88C681 P0.0 (AD0 ...
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... ALE and the use of a 74LS373 transparent latch device can be used to This location is demultiplex the Address and Data bus signals. Figure 5 presents a schematic illustrating how the XR88C681 DUART can be interfaced to the 8051 C. 26 Interrupt Location INT0 ...
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... AD7) ALE PORT 2 (A8 - A15) 8051 CPU Figure 5. An Approach to Interfacing the XR88C681 DUART to the 8051 Microcontroller The circuitry presented Figure 5 would function as follows during a DUART requested interrupt. The DUART device requests an interrupt from the CPU by asserting its active low INTR output pin ...
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CPU, from a external crystal. Controller is responsible for buffering the bi-directional Data Bus. Additionally, since the 8080 CPU device does not directly provide control bus signals, the 8228 Device is responsible for translating signaling information, from the 8080A device, ...
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... Rev. 2.11 Interfacing the 8080 CPU Module to the XR88C681 DUART for Interrupt Processing The 8080A CPU can be connected to the XR88C681 and run in the Interrupt Driven mode. Figure 7 presents an approach that can be applied to interfacing the XR88C681 DUART to the 8080A CPU for “external” ...
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... Figure 7. Circuit Schematic depicting approach to Interface the XR88C681 DUART to the 8080A CPU, for “External” Vectored Interrupt Processing (Interrupt Service Routine resides at 0020 Since the 8080A CPU can support different RST instructions, it can support interrupt-driven peripheral devices. This can be achieved ...
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... A8 A9 A10 A11 A12 A13 A14 A15 However, the user could have just as easily connected the XR88C681 device to the CPU module’s I/O port (e.g, the signal -IOR and -IOW of the CPU module are connected to the -RD and -WR pins of the DUART, respectively IOR - MEMR - ...
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... IO 8085 CPU Figure 9. Schematic of the XR88C681 Interface to the 8085 CPU Module (Memory Mapped). The DUART’s INTR pin was deliberately omitted from - Figure 9, because its use will be addressed in Figure 10 and Figure 11. 8085 CPU Module Interrupt Structure The 8085 CPU supports both Direct and “External” ...
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... Hence, processing are identical to that presented for the 8080 CPU (see Section C.6.1.2). Figure 10 approaches that can be used to interface the XR88C681 DUART to the 8085 CPU. Figure 10 presents a schematic where the DUART will request a “Direct” RST 6.5 Interrupt to the 8085 CPU. In this case, the Interrupt Service Routine for the DUART must begin at 0034 simple interface technique, because there is no “ ...
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... CPU Figure 10. The XR88C681/8085 CPU Interface for Direct Interrupt Processing (Interrupt Service Routine is located at 0034 Figure 11 presents a schematic where the DUART will request a “External-Vectored” Interrupt to the 8085 CPU. In this case, the Interrupt Service Routine for the DUART must begin at 0020 Rev ...
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... AD4 AD5 AD6 AD7 ALE Figure 11. The XR88C681/8085 CPU Interface for Vectored Interrupt Processing (In- terrupt Service Routine is located at 0020 C.6.1.4 68HC11 Microcontroller Motorola manufactures a family of microcontrollers, referred to as the MC68HC11 microcontrollers. This family of microcontrollers offers some of the following amenities Multi-Function Parallel Ports ...
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Figure 12 presents the block diagram of the MC68HC11 C. MODA MODB Mode Control Timer System Port A Figure 12. Block Diagram of the MC68HC11 Microcontroller The 68HC11 can be configured to operate in a “Single Chip” Mode or in ...
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... This port can be configured to function as a general purpose input or as the inputs to the on-chip A/D converter. There are numerous other pins that are pertinent for interfacing to the XR88C681 DUART device. Some of these pins are discussed here. Rev. 2.11 IRQ This is the “maskable” interrupt request input. If this input is asserted (e.g., toggled “ ...
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... E -R/W MODA A8 - A15 MODB -IRQ AS AD0 - AD7 68HC11 Figure 13. XR88C681/MC68HC11 Microcontroller Interfacing Approach Rev. 2.11 Address Decoder 74HC373 38 to other ICs -CS -RD -WR -INTR XR88C681 ...
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... E clock -RESET Figure 14. Glue Logic Circuitry Required to Interface the MC68HC11 C to the XR88C681 DUART C.6.1.5 Z-80 CPU The Z-80 CPU can be interfaced to a DUART operating in the I-Mode (the CPU) is operating in Interrupt Modes However, for the sake of “process or continuity”, the details associated with the Z-80 CPU will be presented in Section C ...
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V CC -INT V CC CPU -IACK Figure 15. A Diagram of Numerous DUARTs Configured in an Interrupt In addition to the INTR and IACK pins, the Z-Mode - - DUART also uses the IEI and IEO pins; which are ...
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... C.6.2.1 Z-80 Microprocessor The Z-80 P consists bit Data Bus bit Address Bus and numerous control pins. The Z- very flexible processor which can actually interface to either a Z-Mode or an I-Mode DUART device. This is because the 41 XR88C681 FLOAT Reset IUS Command The ...
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Z-80 P can be configured to operate in one of three different “interrupt modes”. The Z-80 is also a little bit less complicated to interface to (than some of the P/ Cs The Z-80 CPU will support Read/Write operations between ...
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... CPU module will assert INTA (toggle “low”). - Acknowledge” signal that the CPU module outputs in order to initiate the process of interrupt servicing. When the Z-80 CPU operates in the Interrupt Mode XR88C681 -MEMW -MEMR -IOW -IOR -INTA INT pin of the Z-80 ...
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... DUART (or Zilog peripheral device) will be disabled from generating any interrupt requests to the CPU. An example of this approach is presented Figure 19. In this case the XR88C681 DUART is configured to operate in the Z-Mode and is interfaced to the Z-80 CPU. When the DUART requires interrupt servicing, it will assert its 44 in memory ...
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... Register of the DUART from Vcc or higher priority peripheral Address to lower priority Decoder peripheral Circuitry CS_DUART -MEMW -MEMR -INTA CPU (for Z-Mode Operation) 45 XR88C681 Least Significant Byte Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IEI IEO - -INTR -WR -RD -IACK XR88C681 IACK - Bit 0 0 ...
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C.6.2.2 8086 Microprocessor The 8086 microprocessor bit microprocessor manufactured by Intel Corporation. Figure 20 presents the pin out diagram of this IC. Please note that in Figure 20, pins have some additional labels, located ...
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... Table 15 presents the processor status and 8288 active outputs based on the S2 “max” mode status signals. - Processor State Interrupt Acknowledge Read I/O Port Write I/O Port Halt Code Access Read Memory Write Memory Passive 47 XR88C681 MN (Max Mode) - RQ/ GT0 - - RQ/ GT1 - - LOCK - ...
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Figure 21 and Figure 22 present the 8086 CPU Mode, when operating in the “min” and “max” modes, respectively. INTR -INTA HOLD -DEN DT/-R Vcc MN/-MX 8086 CPU Figure 21. Schematic of the 8086 CPU Mode (Min Mode) Rev. 2.11 ...
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... Routines/Jump Table. Figure 23 presents a schematic of the XR88C681 DUART interfacing to a “min” Mode 8086 CPU device. Please note that the DUART has been configured to operate in the Z-Mode. Therefore, the user must account for the IEI input to the DUART device ...
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... MN 8086 CPU Figure 23. Schematic of the XR88C681 DUART Device Interfacing TIMING CONTROL BLOCK The Timing Control Block allows to the user to specify the bit rates that he/she wishes to transmit and receive data at each channel. The Timing Control Block consists of the following elements: ...
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... MHz and 4 MHz is required for proper operation of the DUART. However, a crystal or TTL signal frequency of 3.6864 MHz is required for the generation of standard bit rates by the Bit Rate Generator (See Table 18). schematic for the XTAL Oscillator circuitry. 51 XR88C681 IP4 IP3 (TXCA) 32:1 MUX 32:1 ...
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... DUART, to the point that the Schmitt Trigger inverter can no longer change state or respond to the oscillator signal. Rev. 2.11 C1: 10pF + (Stray < 5pF) C2: 10pF + (Stray < 5pF) R1: 100ohm R2: 100ohm R1 X1 XR88C681 R2 X2 3.6864MHz Parallel Resonant Crystal XR88C681 3.684MHz 74HC14 inputs of other DUARTs ...
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... ACR[7]. A listing of these sets of Bit Rates, from the BRG, is presented in the discussion of the Clock Select Registers (CSRs) in Section D.5. A block diagram of the BRG circuitry is presented in Figure 27. ACR[7] Bit Rate Generator Channels A and B 53 XR88C681 CSRA[7:4] RXCA 32:1 MUX CSRA[3:0] 32:1 MUX TXCA CSRB[7:4] ...
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D.3 Counter/Timer The Timing Control Block also contains a 16 bit Counter/Timer (C/T). The C programmable 16 bit down-counter which can use one of several timing sources as its input. Figure 28 presents a block diagram of the ...
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... COUNTER READY status bit, in the Interrupt Status Register (ISR[3]), is set once each cycle of the square wave. This allows the use of the C periodic Rev. 2.11 XR88C681 interrupt generator, if the condition is programmed to generate an interrupt via the interrupt mask register (IMR). The ISR[3] can be cleared by issuing the address-triggered “ ...
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Receivers. Table 17 and Table 18 present the relationship between the contents of the CSRs and the clock source driving the Transmitters and Receivers. Bit 7 Bit 6 Receiver Clock Select See Table 18 Table 17. Bit Format of ...
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... Transmitter, and that the Receiver is only sampling the serial data once per bit period. Figure 30 presents the results of this phenomenon. 57 XR88C681 Resulting Action Set Rx BRG Select Extend Bit ( Clear Rx BRG Select Extend Bit ( Set Tx BRG Select Extend Bit ( ...
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Figure 30. Receiver (1X) Sampling, if the RX Clock is Slightly Faster Than the TX Clock Figure 30 shows that the phase relationship between the Receiver’s sampling point and each serial data bit is changing. In this case, the Receiver ...
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... Midpoint of the Bit 1 Bit Period 7- 16X clock periods Figure 32. The Typical Sampling Pattern of Each Receiver Within the XR88C681 Device. Rev. 2.11 XR88C681 factor of 16. However, after 7 16X clock periods has elapsed, the receiver will assume this point (within the START bit the mid point of the bit period, and will cease oversampling of the START bit and of the subsequent data ...
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... The XR88C681 devices gives the user the option to declare an external input clock signal as either 16X clock signal. Whenever the user is given a choice to ...
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... The purpose of this section is to explain the Data Sheet specification on the Timing Control Block parameters. In the past, this subject has been the source of considerable confusion by numerous users. The XR88C681 Data Sheet presents the following parameter specifications in the “AC ELECTRICAL CHARACTERISTICS” Min. ...
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This spec is not related to the parameter tRTX, which also specifies limits on signals applied to IP2 or other input pins, for use at the External Clock Source for Transmitter and Receivers RXC and TXC (External) ...
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... Bit 3 Delta IP0 IP3 Low 1 = Yes 1 = High 63 XR88C681 Approach to Program Alternate Functions IP0 can be programmed to function as the input by setting MR2A[4] =1. For a more detailed discussion on this function, please see Section G.3. IP1 can be programmed to function as the input by setting MR2B[4] =1. For a more detailed discussion on this function, please see Section G ...
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In order to enable the “Input Port Change of State” interrupt, one must do the following. D Write the appropriate data to the lower nibble of ACR. The bit formats for ACR is presented in Table 23. Please note that ...
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... This example of the “SET OUTPUT PORT BITS” command is illustrated in Figure 33 XR88C681 State of Output Port Pins (OP7 - OP0 DUART Address 0Eh ...
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In summary, for the “SET OUTPUT PORT BITS” command results in no change for OPR[n], nor Output Port pin OPn results in OPR[n] = “1”, and Output Port pin, OPn = “0” F.1.2 Clear ...
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... TXRDY_B Output: Channel B Transmitter Ready Indicator. This is an Open-Drain output for the TXRDY_B function. Bit 5 Bit 4 Bit 3 OP5 OP4 0 = OPR[ OPR[ RXRDY C/T #1 Output FFULLA 10 = TXCB (1X RXCB (1X) 67 XR88C681 Bit 2 Bit 1 OP3 OP2 00 = OPR[ TXCA (16X TXCA (1X RXCA (1X) Bit 0 ...
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... OUTPUT PORT BITS” and “CLEAR OUTPUT PORT BITS” commands only effects these two pins. Additionally -RTSA and -RTSB are the only alternative output port pin functions available to this version of the XR88C681. G. SERIAL CHANNELS A and B Each serial channel of the DUART comprises a full-duplex asynchronous receiver and transmitter ...
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... Afterwards, the data is converted to parallel format, and is transferred to the RHR. This character is then processed through the 3 bytes of FIFO. Once the received character reaches the top of the FIFO, it can be “popped” or read by the CPU; when it reads the RHR. Figure 37 depicts a simplified drawing of the Receiver. 69 XR88C681 Stop Bit ...
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Receive Shift Register RXDn Incoming Serial Data Figure 37. A Simplified Drawing of the Receiver Shift Register The receiver functions by sensing the voltage level at the RXDn input. When the far-end transmitter is idle, its TXDn output (and consequently, ...
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... The bits of each of these registers are discussed in Table 26. Bit 4 Bit 3 Parity Mode Select 00 = With Parity 01 = Force Parity Parity 11 = Multi-Drop Mode Table 26. Mode Registers - MR1A, MR1B 71 XR88C681 Bit 2 Bit 1 Bit 0 Select Select Number of Bits per Parity Character 0 = Even Odd ...
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Bit 7 Bit 6 Channel Mode Tx RTS Control 00 = Normal 01 = Auto Echo 10 = Local Loop 11 = Remote Loop MR1n[7] - Receiver Request to Send Control Ordinarily, RTS (Request to Send) is asserted or negated ...
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... Figure 39 presents a diagram de- picting Automatic Echo Mode Operation. The follow- ing conditions apply while in this mode. Figure 38 RXCn TXCn Transmit Shift Register 8 (Parallel data from the CPU) 73 XR88C681 TXDn Outgoing Serial Transmit Holding Register 8 From Data Bus. Data ...
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RXDn Incoming Receive Shift Register Serial Data Receive Holding Register To Data Bus (To be read by the CPU) Figure 39. A Block Diagram Depict Automatic Echo Mode In this mode: 1. Received data is transmitted on the channel’s TXD ...
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... CPU to transmitter and receiver communications continue normally. Rev. 2.11 TXCn Transmit Shift Register 8 (Parallel Data from CPU) Remote Loopback Mode. This mode is selected by setting MR2n[7:6] = 11. Figure 41 presents a diagram depicting Remote Loopback Mode operation. 75 XR88C681 V CC Transmit Holding Register 8 From Data Bus. TXDn ...
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RXDn Incoming Receive Shift Register Serial Data Receive Holding Register Note: The CPU has no access to the Serial Data during Remote Loopback Mode. Figure 41. A Block Diagram Depicting Remote Loopback Mode In this mode: 1. Received data is ...
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... Frame Error (FE). If the Error Mode has been set to “Character” Mode, this bit only applies to the Character at the top of the RHR XR88C681 Bit 2 Bit 1 Bit 0 TXRDY ...
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STOP bit is properly detected in the next character. If the “Error” Mode has been set to “Block” mode, then this bit, once set will remain ...
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... RTS signal if its RHR is full; and, is thereby, very effective in preventing Receiver Overrun Errors. presents a diagram of an example illustrating the operation of the Receiver-Controlled RTS configuration. RTSA (OP0) RXDA TXDA CTSA (IP0) in the Receiver-RTS Controlled Configuration 79 XR88C681 Transmitting Device CTSB (IP1) TXDB RXDB RTSB (OP1) Figure 42 ...
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Figure 42 shows two DUART devices, a “Receiving Device” and a “Transmitting Device”. These devices are labeled such because of their role in this example transfer of data between them. This example is going to ignore, for the time being, ...
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... Transmitter to negatye the RTS signal, one bit period after emptying the THR and TSR. Rev. 2.11 For Receiving Device MR1A[ For Transmitting Device MR2B[ Start “0”.) Is FFULLA Asserted? Yes RTSA is Automatically Negated by Receiver Controlled RTS Function. 81 XR88C681 No Is Yes FFULLA Negated? ...
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Transmitting Device TXRDY_A (OP7) To CPU TXRDY_A RTSA CTSA RXDA Figure 44. Block Diagram and Timing Sequence of Two DUARTs Connected in the Transmitter-RTS Controlled Configuration. Rev. 2.11 RTSA (OP0) CTSA (IP0) TXDA 82 Receiving Device IP2 (RTS-in) OP3 (CTS-out) ...
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... Algorithm that could be used to implement the PORT BITS Transmitter-Control Please note that the shaded block pertain to occurrences within the “Receiving Device”. Whereas the “White” block pertain to operation within the “Transmitting Device.” 83 XR88C681 . In this step, the Interrupt 16 RTS/CTS Handshaking Mode. ...
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START ASSERT RTSA (Write 01h to DUART Address 0Eh) *CTSA INPUT IS ASSERTED. Data transmission is now permitted. Is TXEMT Asserted ? *RTSA is Automatically Negated by Receiver Controlled RTS Function. (OP0 toggles “High”) -CTSA INPUT IS NEGATED. Data transmission ...
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... Address byte that identifies the “Target Slave”. An address byte differs from a data byte in that the ninth bit is a “1” Address Byte and a “0” Data Byte. 85 XR88C681 RXDn FFh Address/Data Bit ...
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An Address Byte, however, interrupts all “Slaves” so that each can examine the received byte to test if it (the individual slave device) is being addressed. The receiver of the addressed slave will be enabled and will prepare for reception ...
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... Newly Received Address match CPU Address ? Enable Receiver (Write x2h to the Appropriate Channel Command Register) Read in Data Character from RHR. Yes Check SRn[5] Is the New Character a No Data Character SRn[ Characters in the Multi-Drop Mode. 87 XR88C681 No Reject Character Receiver remains Disabled Yes Yes ...
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... Active operation can also be restored via hardware reset. I. COMMENTS ABOUT THE XR88C681 IN 28 PIN DIP PACKAGE Much of this data sheet discussed features which are available to the DUARTs which are packaged in the 40 pin DIP or the 44 pin PLCC ...
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... Yes 1 = Yes Table 33. Status Registers: SRA, SRB Bit 4 Bit 3 OP4 0=OPR[ OPR[3] 1=RXRDY C/T #1 Output FFULLA 10 = TXCB (1X RXCB (1X) 89 XR88C681 Bit 2 Bit 1 Stop Bit Length 8h = 1.563 9h = 1.625 Ah = 1.688 Bh = 1.750 Ch = 1.813 Dh = 1.875 Eh = 1.938 Fh = 2.000 Bit 2 Bit 1 Transmitter Clock Select See Table 9 ...
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Bit 7 Bit 6 Bit 5 BRG Set Counter/Timer #1 Mode and Source Select 0 = Set1 See Table Set2 Bit 7 Bit 6 Bit 5 Delta IP3 Delta IP2 Delta IP1 ...
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... Note: AC testing inputs are driven at 0.4V for a logic “0” and 2.4V for a logic “1” except for -40 to 85(C and -55 to 125(C, logic “1” shall be 2.6V. Timing measurements are made at 0.8V for a logic “0” and 2.0V for a logic “1”. RESET Rev. 2.11 2.0V Test Levels 0.8V t RES Figure 51. Reset Timing 91 XR88C681 2.0V 0.8V ...
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... - - FLOAT (Read) - (Write) Figure 52. XR88C681 Read and Write Cycle Timing Rev. 2. RWD NOT VALID VALID t RWD VALID 92 FLOAT ...
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... IAS - FLOAT IEI t DIO t EOD IEO t DIO Figure 53. XR88C681 Z Mode Interrupt Cycle Timing Rev. 2. EIS NOT VECTOR VALID 93 XR88C681 t IAH FLOAT RESET IUS COMMAND ...
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PS IP0 - IP6 -WR or -CS OP0 - OP7 -RD or -CS or -WR Interrupt Output Rev. 2. OLD DATA t PD Figure 54. Port Timing t IR Figure 55. Interrupt Timing 94 ...
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... C2: 10pF + (Stray < 5pF) R1: 100ohm R2: 100ohm C1 C2 3.6864MHz Parallel Resonant Crystal X1/CLK C/T CLK RXC TXC Rev. 2. XR88C681 CLK t CTC t RTX t CLK t CTC t RTX Figure 56. Clock Timing 95 XR88C681 C1 15pF + (Stray < 5pF) C2 5pF + (Stray < 5pF XR88C681 C2 X2 3.6864MHz Parallel Resonant Crystal ...
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TXC (Input) t TXD TXD TXC (1X Output) RXC 1X Input) RXD Rev. 2.11 1 Bit Time ( Clocks) t TCS Figure 57. Transmitter Timing t t RXS RXH Figure 58. Receiver Timing 96 ...
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... BSC 1.27 BSC 0.042 0.056 1.07 0.042 0.048 1.07 0.025 0.045 0.64 97 XR88C681 C Seating Plane 45° MAX 4.57 3.05 ------ 0.53 0.81 0.32 17.65 16.66 16.00 1.42 1.22 1.14 ...
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LEAD CERAMIC DUAL-IN-LINE Base 1 Plane Seating L Plane B SYMBOL Note: The control dimension is the inch column Rev. 2.11 (600 MIL CDIP) Rev. ...
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... MILLIMETERS MIN MAX MIN MAX 0.160 0.250 4.06 6.35 0.015 0.070 0.38 1.78 0.125 0.195 3.18 4.95 0.014 0.024 0.36 0.56 0.030 0.070 0.76 1.78 0.008 0.014 0.20 0.38 1.380 1.565 35.05 39.75 0.600 0.625 15.24 15.88 0.485 0.580 12.32 14.73 0.100 BSC 2.54 BSC 0.600 BSC 15.24 BSC 0.600 0.700 15.24 17.78 0.115 0.200 2.92 5.08 0° 15° 0° 15° 99 XR88C681 ...
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A Seating Plane L B Rev. 2.11 40 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) Rev. 1. INCHES SYMBOL MIN MAX A 0.160 0.250 A 0.015 0.070 1 A 0.125 0.195 2 B 0.014 0.024 B 0.030 ...
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... EXAR Corporation is adequately protected under the circum- stances. Copyright 2006 EXAR Corporation Datasheet June 2006 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.11 Revision History (June 2006) Corrected pinout on 28--pin PDIP package on page 3 (pin 1 is A0). Added Revision History. NOTICE 101 XR88C681 ...