XR88C681CP/40-F Exar Corporation, XR88C681CP/40-F Datasheet - Page 30

• Manufacturer Part Number: XR88C681CP/40-F
• Description: IC UART CMOS DUAL 40PDIP
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681CP/40-F

• Number Of Channels: 2, DUART
• Package / Case: 40-DIP (0.600", 15.24mm)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Filter Terminals: DIP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1328-5

Since the 8080A CPU can support up to 8 different RST
instructions,
interrupt-driven peripheral devices. This can be achieved
by replicating the approach, presented in Figure 7, and
by hardwiring the op-codes for each of the RESTART
instructions to the inputs of the Data Buffers (see
Table 10).
These Data Buffers should be enabled only during the
-INTA cycle, and only when their associated peripheral
requested the interrupt service.
C.6.1.3 8085 Microprocessor
The 8085 CPU is another early Intel microprocessor,
although it is more advanced than the 8080A CPU. Some
Rev. 2.11
8080A CPU
U1
it
Figure 7. Circuit Schematic depicting approach to Interface the XR88C681 DUART
can
DBIN
INTE
D0
D1
D2
D3
D4
D5
D6
D7
INT
support
to the 8080A CPU, for “External” Vectored Interrupt Processing
(Interrupt Service Routine resides at 0020
up
to
Bi-Directional
BUS Driver
8228
8
different
U2
INTA
U5
30
of the advancements that were made in the transition
from the 8080A to the 8085 include combining the Clock
Generator functions of the 8224 onto the CPU chip,
adding a non-maskable interrupt request, adding 3
“direct” interrupt request input pins, and adding some
form of interrupt priority. The 8085 still requires some glue
logic in order to produce the Control Bus signals (i.e.,
-IOR, -IOW, -MEMR, -MEMW).
minimize pin count, the 8085 contains a multiplexed
Address/Data Bus (AD0 - AD7). Specifically, the lower 8
bits of the Address Bus share pins with the 8 bit Data Bus.
Hence, a 74LS373 8-bit latch is needed in order to
demultiplex the Address and Data buses.
U3
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
-
OE1
SN74LS244
Vcc
-
16
OE2
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
U6
in Memory)
V
cc
Further, in order to
-
INTR
XR88C681
DUART
U4