78P2351-IGT/F Maxim Integrated Products, 78P2351-IGT/F Datasheet - Page 8

• Manufacturer Part Number: 78P2351-IGT/F
• Description: LINE INTERFACE UNIT 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 78P2351-IGT/F

• Number Of Channels Per Chip: 1
• Propagation Delay Time: 10 ns
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LOOPBACK MODES
In SW mode, LLBK and RLBK bits in the Signal
Control register are provided to activate the local
and remote analog loopback modes respectively.
In HW mode, the LPBK pin can be used to activate
local and remote analog loopback paths as shown in
the table below.
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SOCKP/N
SICKP/N
PO[3:0]D
LPBK pin
SODP/N
PI[3:0]D
PTOCK
SIDP/N
POCK
PICK
Float
High
Low
SOCKP/N
SICKP/N
PO[3:0]D
SODP/N
PI[3:0]D
SIDP/N
PTOCK
POCK
PICK
Lock Detect
Figure 8: Remote (Analog) Loopback
Tx CDR
Figure 7: Local (Analog) Loopback
Lock Detect
Loopback Mode
Normal operation
Remote (analog) Loopback:
Recovered receive clock and data
looped back directly to the transmit
driver. The CMI decoder and most of
transmit path is bypassed (including the
redundant Tx monitor output)
Local (analog) Loopback:
Transmit clock and data looped back to
receiver at the analog media interface.
Tx CDR
Decoder
CMI
PMOD, SMOD[1:0], PAR
Decoder
FIFO
Lock Detect
CMI
Rx CDR
PMOD, SMOD[1:0], PAR
FIFO
Lock Detect
CMI
Rx CDR
Encoder
CMI
CMI
Adaptive
Eq.
Encoder
CMI
LOS Detect
Adaptive
Eq.

RLBK,
RDSL
2006 Teridian Semiconductor Corporation
LOS Detect
LLBK
RLBK,
RDSL
ECLP/N
TXCKP/N
CMI2P/N
CMIP/N
RXP/N
LLBK
ECLP/N
TXCKP/N
CMI2P/N
CMIP/N
RXP/N
In SW mode only, a Full Remote (digital) Loopback
bit FLBK is also available in the Advanced Tx
Control register. This loopback exercises the entire
Rx and Tx paths of the 78P2351 including the Tx
clock recovery unit. As such, the user must enable
either Serial Plesiochronous or Serial Loop-timing
transmit modes to utilize the Full Remote (digital)
Loopback.
INTERNAL POWER-ON RESET
Power-On Reset (POR) function is provided on chip.
Roughly 50 µs after Vcc reaches 2.4V at power up,
a reset pulse is internally generated. This resets all
registers to their default values as well as all state
machines within the transceiver to known initial
values. The reset signal is also brought out to the
PORB pin.
analog pin that allows for the following:
•
•
•
NOTE: Do not pull-up the PORB pin to Vcc or drive
this pin high during power-up. This will prevent the
internal reset generator from resetting the entire chip
and may result in errors.
SOxCKP/N
POx[3:0]D
SIxCKP/N
SOxDP/N
PIx[3:0]D
SIxDP/N
PTOxCK
POxCK
PIxCK
Override the internal POR signal by driving in
an external active low reset signal;
Use the internally generated POR signal to
trigger other resets;
Add external capacitor to slow down the
release of power-on reset (approximately 8µs
per nF added).
Figure 9: Remote (Digital) Loopback
Lock Detect
Tx CDR
The PORB pin is a special function
Decoder
CMI
PMOD, SMOD[1:0], PAR
FIFO
Lock Detect
Rx CDR
EACH CHANNEL: Tx
EACH CHANNEL: Rx
OC-3/ STM1-E/ E4 LIU
CMI
Encoder
CMI
Single Channel
Adaptive
Eq.
LOS Detect
78P2351
RLBK
LLBK
Rev. 2.4
ECLxP/N
TXxCKP/N
CMIxP/N
RXxP/N