78P2351-IGT/F Maxim Integrated Products, 78P2351-IGT/F Datasheet - Page 18
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78P2351-IGT/F
Manufacturer Part Number
78P2351-IGT/F
Description
LINE INTERFACE UNIT 100-LQFP
Manufacturer
Maxim Integrated Products
Specifications of 78P2351-IGT/F
Number Of Channels Per Chip
1
Propagation Delay Time
10 ns
Supply Voltage (max)
3.45 V
Supply Voltage (min)
3.15 V
Maximum Operating Temperature
+ 85 C
Package / Case
LQFP-100
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
78P2351-IGT/F
Manufacturer:
VISHAY
Quantity:
14 105
Company:
Part Number:
78P2351-IGT/F
Manufacturer:
MAXIM
Quantity:
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Company:
Part Number:
78P2351-IGT/F
Manufacturer:
Maxim Integrated
Quantity:
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RECEIVER PINS
NAME
PO0D
PO1D
PO2D
PO3D
POCK
SODP
SODN
SOCKP
SOCKN
RXP
RXN
Page: 18 of 42
PIN DESCRIPTION
PIN
41
40
37
36
33
20
21
18
19
90
91
TYPE
(continued)
CO
CO
PO
PO
A/
PI
DESCRIPTION
Receive Data (Parallel Mode) Output:
Recovered receive data de-serialized into four-bit CMOS parallel (nibble)
outputs. The MSB (PO3D) is received first. Active, but undefined during
reset.
Note: During Loss of Signal conditions, data outputs are held low.
Receive (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output generated by
dividing down the recovered receive clock. By default, receive data is
clocked out on the falling edge. Active during reset.
Note: During Loss of Signal conditions, the clock will remain on the last
divided down phase selection of the Rx DLL and output a steady clock.
Receive (Serial Mode) Data Output:
Recovered receive serial NRZ data at LVPECL levels. Active, but undefined
during reset.
Note: During Loss of Signal conditions, data outputs are held at logic 0.
Receive (Serial Mode) Clock Output:
Recovered receive serial clock. By default, recovered serial NRZ data is
clocked out the falling edge of SOCKP. Active during reset.
Note: During Loss of Signal conditions, the clock will remain on the last
phase selection of the Rx DLL and output a steady clock.
Receiver (CMI or NRZ) Input:
The input is either transformer-coupled to coaxial cable for CMI data or AC-
coupled at LVPECL levels to an optical transceiver module for NRZ data.
2006 Teridian Semiconductor Corporation
OC-3/ STM1-E/ E4 LIU
Single Channel
78P2351
Rev. 2.4