78P2351-IGT/F Maxim Integrated Products, 78P2351-IGT/F Datasheet - Page 6

• Manufacturer Part Number: 78P2351-IGT/F
• Description: LINE INTERFACE UNIT 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 78P2351-IGT/F

• Number Of Channels Per Chip: 1
• Propagation Delay Time: 10 ns
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Plesiochronous Tx Serial Mode
Figure 3 represents a common condition where a
serial transmit clock is not available and/or the data
is not source synchronous to the reference clock
provided to the 78P2351.
78P2351 will recover a transmit clock from the serial
plesiochronous data and bypass the internal FIFO
and re-timing block. This mode is commonly used
for mezzanine cards, modules, and any application
where
synchronous to the transmit source clock/data.
Synchronous Parallel Modes
In parallel modes, 4-bit CMOS data segments are
input to the chip with a 34.816MHz (E4 ÷ 4) or
38.88MHz (STM1 ÷ 4) synchronous clock. These
inputs are re-timed in a 4x8 clock decoupling FIFO
and then to a serializer for transmission. Because
the data is passed through the FIFO and re-timed
using a synthesized clock, the transmit nibble clock
and data must be source synchronous to the
provided reference clock.
For maximum compatibility with legacy ASICs, the
78P2351 can operate in both slave and master clock
modes as shown in Figures 4 and 5 respectively.
Page: 6 of 42
Parallel
Mode
Slave
Slave +
*Loop-timing
Master
*To enable
SMOD[1:0]=11
Reference
Framer/
Mapper
Clock
Note: A loop-timing mode is also available to
allow external remote loopbacks (i.e. line
loopback in framer). In this mode, the FIFO is
still enabled, but the transmit data will be re-
timed using the recovered receive clock.
the
Figure 3: Plesiochronous data only
(Tx CDR enabled, FIFO bypassed)
HW Control Pins
SDI_PAR
140 / 155 MHz
reference
High
High
High
NRZ
NRZ
loop-timing
SIDP/N
SOCKP/N
SODP/N
CKMODE
Float
High
Low
clock
CKREFP
78P2351
in
TDK
In this mode, the
software
can’t
SW Control Bits
XO
CMIP/N
RXP/N
PAR
1
1
1

CMI
CMI
always
2006 Teridian Semiconductor Corporation
mode,
XFMR
XFMR
PMODE
0
0
1
Coax
Coax
set
be
Transmit FIFO Description
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The transmit FIFO allows long-term clock phase drift
between the Tx clock and system reference clock,
not exceeding +/- 25.6ns, to be handled without
transmit error.
specified limits, the FIFO will over or under flow, and
the FERR register signal will be asserted.
signal can be used to trigger an interrupt.
interrupt event is automatically cleared when a FIFO
Reset (FRST) pulse is applied, and the FIFO is re-
centered.
Reference
Reference
Framer/
Mapper
Framer/
Mapper
Clock
Clock
Notes:
1) External remote loopbacks (i.e. loopback
2) During IC power-up or transmit power-up,
within
synchronous
unless the data is re-justified to be
synchronous to the system reference clock
or the 78P2351 is configured for loop-timing
operation.
the clocks going to the FIFO may not be
stable and cause the FIFO to overflow or
underflow.
manually reset using FRST anytime the
transmitter is powered-up.
4-bit CMOS TTL
Figure 5: Master Parallel Mode
4-bit CMOS TTL
Figure 4: Slave Parallel Mode
4-bit CMOS TTL
4-bit CMOS TTL
34/39 MHz
34/39 MHz
34/39 MHz
34/39 MHz
framer)
If the clock wander exceeds the
As such, the FIFO should be
PI[3:0]D
PIxCK
PO[3:0]D
POCK
operation
OC-3/ STM1-E/ E4 LIU
PI[3:0]D
PTOCK
PO[3:0]D
POCK
are
CKREFP/N
78P2351
CKREFP/N
78P2351
TDK
TDK
Single Channel
not
CMIP/N
RXP/N
(FIFO
CMIP/N
RXP/N
CMI
CMI
possible
78P2351
CMI
CMI
enabled)
XFMR
XFMR
XFMR
XFMR
Rev. 2.4
This
This
Coax
Coax
in
Coax
Coax