78P2351-IGT/F Maxim Integrated Products, 78P2351-IGT/F Datasheet - Page 20

• Manufacturer Part Number: 78P2351-IGT/F
• Description: LINE INTERFACE UNIT 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 78P2351-IGT/F

• Number Of Channels Per Chip: 1
• Propagation Delay Time: 10 ns
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CONTROL PINS
Page: 20 of 42
NAME
FRST
RCSL
LPBK
CKMODE
PIN DESCRIPTION
PIN
59
14
15
13
TYPE
CID
CIT
CIT
CIT
(continued)
DESCRIPTION
FIFO Phase-Initialization Control:
When asserted, the transmit FIFO pointers are reset to the respective
“centered” states. Also resets the FIERR interrupt bit. De-assertion edge of
FRST will resume FIFO operation.
Because the internal VCO clock and off-chip transmit clocks may not be stable
during transmit power-up, it is recommended to always reset the FIFOs after
powering up the IC or the transmitter.
Not valid during Plesiochronous Serial Mode.
Redundant Channel Selection:
Enables the redundant Transmit Monitor Output at pins CMI2P/N.
Analog Loopback Selection:
Clock Mode Selection:
Selects the method of inputting transmit data into the chip. See
TRANSMITTER OPERATION section for more information.
In PARALLEL mode (SDI_PAR high):
In SERIAL mode (SDI_PAR low):
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
Low: FRST assertion.
Float/High: Normal
Low: Normal operation (CMIP/N active only)
High: Transmit Monitor Mode (CMIP/N and CMI2P/N active)
Low: Normal operation
Float: Remote Loopback Enable: Recovered receive data and clock
are looped back to the transmitter for retransmission.
High: Local Loopback Enable: The serial transmit data is looped back
and used as the input to the receiver.
Low: Parallel transmit clock is input to the 78P2351.
Float: Parallel transmit clock is input to the 78P2351. Loop-timing
High: Parallel transmit clock is output from the 78P2351
Low: Reference clock is synchronous to transmit clock and data. Data
is clocked in with SICKP/N and passed through a FIFO
Float: Reference clock is synchronous to transmit data. Clock is
recovered with a CDR and data is passed through a FIFO
High: Reference clock is plesiochronous to transmit data. Clock is
recovered with a CDR and the FIFO is bypassed
2006 Teridian Semiconductor Corporation
mode enabled.
OC-3/ STM1-E/ E4 LIU
Single Channel
78P2351
Rev. 2.4