MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 383

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

If the transmitter is reset through a software command, operation stops immediately (see
“UART Command Registers
operation after a disable or software reset.
If the clear-to-send operation is enabled, CTS must be asserted for the character to be transmitted. If CTS
is negated in the middle of a transmission, the character in the shift register is sent and TxD remains in
mark state until CTS is reasserted. If the transmitter is forced to send a continuous low condition by issuing
a
If the transmitter is programmed to automatically negate RTS when a message transmission completes,
RTS must be asserted manually before a message is sent. In applications in which the transmitter is
disabled after transmission is complete and RTS is appropriately programmed, RTS is negated one bit time
after the character in the shift register is completely transmitted. The transmitter must be manually
reenabled by reasserting RTS before the next message is to be sent.
The transmitter must be enabled prior to accepting a
while the BREAK is active, the BREAK is not terminated. The BREAK can only be terminated by using
the
Figure 16-25
Freescale Semiconductor
START BREAK
USRn[TxRDY]
STOP BREAK
Transmitter
Enabled
internal
module
1
2
3
4
select
Cn = transmit characters
W = write
UMR2n[TxCTS] = 1
UMR2n[TxRTS] = 1
CTS
RTS
TxD
shows the functional timing information for the transmitter.
3
4
command, the transmitter ignores the state of CTS.
command.
MCF5272 ColdFire
Manually asserted
by
C1
W
BIT
2
1
-
SET
(UCRn)”). The transmitter is reenabled through the UCRn to resume
C1
1
command
C1 in transmission
C2
W
Figure 16-25. Transmitter Timing
®
Integrated Microprocessor User’s Manual, Rev. 3
C2
C3
W
break
Start
START BREAK
W
C3
Break
command. If the transmitter is disabled
C4 Stop
W
break
W
transmitted
C4
not
C5
W
Section 16.3.5,
Manually
asserted
UART Modules
C6
W
C6
16-23