MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 158

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Debug Support
5.7.2
The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown
below. The PST/DDATA specification for these opcodes is shown in
The move-to-SR and RTE instructions include an optional PST = 0x3 value, indicating an entry into user
mode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode, a
multiple-cycle status of 0xD is signaled.
Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted state (PST = 0xF)
display this status throughout the entire time the ColdFire processor is in the given mode.
5-40
Instruction
move.w
move.w
wdebug
cpushl
movec
stop
halt
rte
Supervisor Instruction Set
Operand Syntax
Table 5-23. PST/DDATA Specification for Supervisor-Mode Instructions
{Dy,#imm},SR
SR,Dx
<ea>y
Ry,Rc
#imm
MCF5272 ColdFire
operand},
PST = 0x1
PST = 0x1,
PST = 0xF
PST = 0x1
PST = 0x1, {PST = 0x3}
PST = 0x1
PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 3}, { PST =0xB, DD =source
PST = 0x5, {[PST = 0x9AB], DD = target address}
PST = 0x1,
PST = 0xE
PST = 0x1, {PST = 0xB, DD = source, PST = 0xB, DD = source}
®
Integrated Microprocessor User’s Manual, Rev. 3
PST/DDATA
Table
5-23.
Freescale Semiconductor