MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 226

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Ethernet Module
11.4.4
The hash table process used in the group hash filtering operates as follows. When a frame with the
destination address I/G bit set is received by the FEC, the 48-bit destination media access control (MAC)
address is mapped into one of 64 bins, which are represented by 64 bits stored in HTLR and HTUR. This
is performed by passing the 48-bit MAC address through the on-chip 32-bit CRC generator and selecting
6 bits of the CRC-encoded result to generate a number between 0 and 63. Bit 31 of the CRC result selects
HTUR (bit 31 = 1) or HTLR (bit 31 = 0). Bits 30–26 of the CRC result select the bit within the selected
register. If the CRC generator selects a bit that is set in the hash table, the frame is accepted; otherwise, it
is rejected. The result is that if eight group addresses are stored in the hash table and random group
addresses are received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from
reaching memory. Those that do reach memory must be further filtered by the processor to determine if
they truly contain one of the eight preferred addresses.
The effectiveness of the hash table declines as the number of addresses increases.
The hash table registers must be initialized by the user. The CRC32 polynomial to use in computing the
hash is as follows:
11.4.5
The minimum interpacket gap time for back-to-back transmission is 96 bit times. After completing a
transmission or after the backoff algorithm completes, the transmitter waits for carrier sense to negate
before starting its interpacket gap time counter. Frame transmission may begin 96 bit times after carrier
sense is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit
times, it is ignored and a collision will occur.
The receiver receives back-to-back frames separated by at least 28 bit times. If an interpacket gap between
receive frames is less than 28 bit times, the following frame may be discarded by the receiver.
11.4.6
If a collision occurs during transmission, the FEC continues transmitting for at least 32 bit times, sending
a JAM pattern of 32 ones. The JAM pattern follows the preamble sequence if the collision occurs during
preamble.
If a collision occurs within 64 byte times, the retry process is initiated. The transmitter waits a random
number of slot times. A slot time is 512 bit times. If a collision occurs after 64 byte times, no
retransmission is performed and the end-of-frame buffer is closed with an LC error indication.
11.4.7
Both internal and external loopback are supported by the FEC. In loopback mode, both of the FIFOs are
used and the FEC actually operates in a full-duplex fashion. Both internal and external loopback are
configured using combinations of RCR[LOOP].
For internal loopback, set LOOP and clear DRT. E_TxEN and E_TxER cannot assert during internal
loopback.
For external loopback, clear LOOP, set DRT, and configure the external transceiver for loopback.
11-8
Hash Table Algorithm
Interpacket Gap Time
Collision Handling
Internal and External Loopback
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