MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 336

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Physical Layer Interface Controller (PLIC)
13.6.4
In this example, port 0 is not used. The port 0 pins are multiplexed with UART0 and in this example, port 0
is used to connect to an external transceiver to provide an RS232 interface. Port 1 is programmed in slave
mode and an external U (or S/T) transceiver is connected to port 1. Port 2 and port 3 are used to connect
up to four external PCM CODECs.
In the above example, Freescale’s MC14LC5480 CODECs and MC145572 U transceiver are shown. The
U transceiver in this example is connected to port 1 and the FSC1 frame sync signal is used exclusively
for synchronizing the data on the U transceiver’s IDL interface. CODECs 1 and 2 are connected to delayed
frame sync 2, DFSC2, which is the output of programmable delay 2. Programmable delay 2 generates a
delayed frame sync with reference to FSC1. Similarly CODECs 3 and 4 are connected to DFSC3 which is
the output of programmable delay 3. Programmable delay 3 generates a delayed frame sync also with
reference to FSC1. The MC14LC5480 CODECs, when in IDL mode, may be programmed using the FSR
pin to select whether the CODEC is receiving and transmitting on the B1 or the B2 time slot (see
MC14LC5480 data sheet for further information).
Figure 13-40
IDL2 10-bit mode with a common frame sync.
13-40
Example 2: ISDN SOHO PBX with Ports 1, 2, and 3
shows the IDL bus timing relationship of the CODECs and U transceiver when in standard
MCF5272
MCF5272 ColdFire
Interface1
Figure 13-39. ISDN SOHO PABX Example
UART0
DFSC2
DFSC3
Dout1
FSC1
DCL1
Din1
®
Integrated Microprocessor User’s Manual, Rev. 3
Tx
Rx
IDL SYNC
DT
DT
IDL CLK
DT
DT
DR
DR
DR
FST
DR
FST
BCLKT
FST
BCLKT
BCLKT
FST
BCLKT
RS232
Transceiver
MC14LC5480
MC14LC5480
MC14LC5480
MC14LC5480
MC145572
CODEC 1
CODEC 2
CODEC 3
CODEC 4
BCLKR
BCLKR
BCLKR
BCLKR
FSR
FSR
FSR
FSR
Vdd
GND
Vdd
Vdd
Vdd
GND
Freescale Semiconductor