MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 123

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Another example of a variant branch instruction would be a JMP (A0) instruction.
the PST and DDATA outputs that indicate when a JMP (A0) executed, assuming the CSR was programmed
to display the lower 2 bytes of an address.
PST of 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Thus, the
subsequent 4 nibbles of DDATA display the lower 2 bytes of address register A0 in
least-to-most-significant nibble order. The PST output after the JMP instruction completes depends on the
target instruction. The PST can continue with the next instruction before the address has completely
displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured
values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO.
5.4
In addition to the existing BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contains nine registers to support the required functionality. These registers
are also accessible from the processor’s supervisor programming model by executing the WDEBUG
instruction (write only). Thus, the breakpoint hardware in the debug module can be read or written by the
external development system using the debug serial interface or by the operating system running on the
processor core. Software is responsible for guaranteeing that accesses to these resources are serialized and
logically consistent. Hardware provides a locking mechanism in the CSR to allow the external
development system to disable any attempted writes by the processor to the breakpoint registers (setting
CSR[IPW]). BDM commands must not be issued if the MCF5272 is using the WDEBUG instruction to
access debug module registers or the resulting behavior is undefined.
These registers, shown in
implemented bits.
Freescale Semiconductor
PSTCLK
DDATA
PST
Programming Model
MCF5272 ColdFire
Figure 5-3. Example JMP Instruction Output on PST/DDATA
0x5
0x0
Figure
5-4, are treated as 32-bit quantities, regardless of the number of
0x9
0x0
®
Integrated Microprocessor User’s Manual, Rev. 3
default
A[3:0]
default
A[7:4]
A[11:8]
default
Figure 5-3
A[15:12]
default
shows when
Debug Support
5-5