MCF5272VF66 Freescale Semiconductor, MCF5272VF66 Datasheet - Page 524

• Manufacturer Part Number: MCF5272VF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

List of Memory Maps
A-8
0x030C
0x031C
0x032C
0x033C
0x035C
0x036C
0x037C
0x0300
0x0304
0x0308
0x0310
0x0314
0x0318
0x0320
0x0328
0x0330
0x0334
0x0338
0x0340
0x0344
0x0348
0x0350
0x0354
0x0358
0x0360
0x0364
0x0368
0x0370
0x0374
0x0378
0x0383
0x0384
0x0388
MBAR
Offset
Port0 GCI C/I RX (P0GCIR) Port1 GCI C/I RX (P1GCIR) Port2 GCI C/I RX (P2GCIR) Port3 GCI C/I RX (P3GCIR)
Port0 GCI C/I TX (P0GCIT) Port1 GCI C/I TX (P1GCIT) Port2 GCI C/I TX (P2GCIT) Port3 GCI C/I TX (P3GCIT)
Port 0 D Data Transmit
Port 0 D Data Receive
Port0 Interrupt Configuration Register (P0ICR)
Port2 Interrupt Configuration Register (P2ICR)
Port0 GCI/IDL Configuration Register (P0CR)
Port2 GCI/IDL Configuration Register (P2CR)
Reserved
(P0DRR)
(P0DTR)
[31:24]
Port0 GCI Monitor RX (P0GMR)
Port2 GCI Monitor RX (P2GMR)
Port0 GCI Monitor TX (P0GMT)
Port2 GCI Monitor TX (P2GMT)
Port0 Periodic Status (P0PSR)
Port2 Periodic Status (P2PSR)
MCF5272 ColdFire
Table A-14. PLIC Module Memory Map
Port 1 D Data Transmit
GCI Monitor TX Status
Port 1 D Data Receive
®
Integrated Microprocessor User’s Manual, Rev. 3
Reserved
Reserved
(PGMTS)
(P1DRR)
(P1DTR)
[23:16]
Port0 B1 Data Receive (P0B1RR)
Port1 B1 Data Receive (P1B1RR)
Port2 B1 Data Receive (P2B1RR)
Port3 B1 Data Receive (P3B1RR)
Port0 B2 Data Receive (P0B2RR)
Port1 B2 Data Receive (P1B2RR)
Port2 B2 Data Receive (P2B2RR)
Port3 B2 Data Receive (P3B2RR)
Port0 B1 Data Transmit (P0B1TR)
Port1 B1 Data Transmit (P1B1TR)
Port2 B1 Data Transmit (P2B1TR)
Port3 B1 Data Transmit (P3B1TR)
Port0 B2 Data Transmit (P0B2TR)
Port1 B2 Data Transmit (P1B2TR)
Port2 B2 Data Transmit (P2B2TR)
Port3 B2 Data Transmit (P3B2TR)
Port 2 D Data Transmit
Port 2 D Data Receive
GCI Monitor TX abort
Port1 Interrupt Configuration Register (P1ICR)
Port3 Interrupt Configuration Register (P3ICR)
Port1 GCI/IDL Configuration Register (P1CR)
Port3 GCI/IDL Configuration Register (P3CR)
(P2DRR)
(PGMTA)
(P2DTR)
[15:8]
Port1 GCI Monitor RX (P1GMR)
Port3 GCI Monitor RX (P3GMR)
Port1 GCI Monitor TX (P1GMT)
Port3 GCI Monitor TX (P3GMT)
Port1 Periodic Status (P1PSR)
Port3 Periodic Status (P3PSR)
Port 3 D Data Transmit
Port 3 D Data Receive
GCI D-Channel Status
Freescale Semiconductor
GCI C/I TX Status
(PGCITSR)
Reserved
(PDCSR)
(P3DRR)
(P3DTR)
[7:0]