SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 33

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
Architectural Overview
3.2
On-Chip System Resources
C161U controllers provide a number of powerful system resources designed around the
CPU. The combination of CPU and these resources results in the high performance of
the members of this controller family.
Peripheral Event Controller (PEC) and Interrupt Control
The Peripheral Event Controller allows to respond to an interrupt request with a single
data transfer (word or byte) which only consumes one instruction cycle and does not
require to save and restore the machine status. Each interrupt source is prioritized every
machine cycle in the interrupt control block. If PEC service is selected, a PEC transfer is
started. If CPU interrupt service is requested, the current CPU priority level stored in the
PSW register is tested to determine whether a higher priority interrupt is currently being
serviced. When an interrupt is acknowledged, the current state of the machine is saved
on the internal system stack and the CPU branches to the system specific vector for the
peripheral.
PEC contains a set of SFRs which store the count value and control bits for eight data
transfer channels. In addition, the PEC uses a dedicated area of RAM which contains
the source and destination addresses. The PEC is controlled similar to any other
peripheral through SFRs containing the desired configuration of each channel.
An individual PEC transfer counter is implicitly decremented for each PEC service
except forming in the continuous transfer mode. When this counter reaches zero, a
standard interrupt is performed to the vector location related to the corresponding
source. PEC services are very well suited, for example, to move register contents to/from
a memory table. C161U has 8 PEC channels each of which offers such fast interrupt-
driven data transfer capabilities.
Memory Areas
The memory space of the C161U is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which covers up to 2 MBytes. The entire memory space can
be accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bit addressable.
A 16-bit wide internal RAM (IRAM) provides fast access to General Purpose Registers
(GPRs), user data (variables) and system stack. The internal RAM may also be used for
code. A unique decoding scheme provides flexible user register banks in the internal
memory while optimizing the remaining RAM for user data. The size of the internal RAM
is 3 KByte.
The CPU disposes of an actual register context consisting of up to 16 wordwide and/or
bytewide GPRs, which are physically located within the on-chip RAM area. A Context
Pointer (CP) register determines the base address of the active register bank to be
Data Sheet
33
2001-04-19