SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 197

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Note: BUSCON0 is initialized with 0000
Data Sheet
Bit
MTTCx
EWENx
BTYPx
ALECTLx
BUSACTx
RDYENx
CSRENx
CSWENx
during reset, bits BUSACT0 and ALECTL0 are set (‘1’) and bit field BTYP is loaded
with the bus configuration selected via PORT0.
Early Write Enable Bit
External Bus Configuration
ALE Lengthening Control
Bus Active Control
READY Input Enable
Read Chip Select Enable
Function
Memory Tristate Time Control
‘0’: 1 waitstate
‘1’: No waitstate
‘0’: Normal write
‘1’: Early write is enabled. The write signal turns off one TCL earlier.
In order to have no overlapping with the following ALE signal, the write
control signal is shortened by one TCL by setting bit EWEN.
0 0 : 8-bit Demultiplexed Bus
0 1 : 8-bit Multiplexed Bus
1 0 : 16-bit Demultiplexed Bus
1 1 : 16-bit Multiplexed Bus
Note: For BUSCON0 BTYP is defined via PORT0 during reset.
‘0’: Normal ALE signal
‘1’: Lengthened ALE signal
‘0’: External bus disabled
‘1’: External bus enabled (within the respective address window, see
ADDRSEL)
‘0’: External bus cycle is controlled by bit field MCTC only
‘1’: External bus cycle is controlled by the READY input signal
‘0’: The CS signal is independent of the read command (RD)
‘1’: The CS signal is generated for the duration of the read command
Write Chip Select Enable
‘0’: The CS signal is independent of the write command (WR,WRL,WRH)
‘1’: The CS signal is generated for the duration of the write command
H
, if pin EA is high during reset. If pin EA is low
197
External Bus Interface
2001-04-19
C161U