SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 12

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
• USB Interface including:
• On-Chip PLL for CPU and USB clock generation
• External crystal and direct driven input clock of 8 MHz when USB interface is used. In
• Single and variable crystal clock input frequency (using USB 8 MHz only)
• Bootstrap Loader support via USART interface
• On-Chip Debug Support (OCDS)
• JTAG Boundary Scan Test Support according to IEEE 1149.1
• 3.3 V Single Supply Voltage, 5 V (TTL-) Tolerant I/Os
• -40 °C to +85 °C operating temperature range
• C161U is available in a 100-Pin P-TQFP package
– Peripheral Event Controller (PEC) for 8 independent DMA channels
– 16 Dynamically Programmable Priority-Level Interrupt System
– Two External Interrupts
– Up to 56 SW-configurative Input/Output (I/O) Ports, some with Interrupt Capabilities
– 8-bit or 16-bit External Data Bus
– Multiplexed or Demultiplexed Address/Data Bus
– Up to 2-Mbyte Linear Address Space for Code and Data
– Four Programmable Chip-Select Lines with Wait-State Generator Logic
– On-Chip 3,072-Byte Dual-Port SRAM for user applications
– On-Chip 1,024-Byte Special Function Register Area
– On-Chip PLL with Output Clock Signal
– Five Multimode General Purpose Timers
– On-Chip Programmable Watchdog Timer
– Glueless Interface to EPROM, Flash EPROM and SRAM
– Low-Power Management Supporting Idle-, Power-Down- and Sleep-Mode and
– USART interface with Auto Baud Rate detection up to 230,400 kbit/s
– USART Baud Rate generation in asynchronous mode up to 2.25 MBaud @ 36 MHz
– USART Baud Rate generation in synchronous mode up to 4.5 MBaud @ 36 MHz
– USART standard Baud Rates generation with very small deviation (230.4 kBaud
– High speed Serial Synchronous Channel Interface (SSC) with ALIS-3.0 and AC97
– USB Specification 1.1 Compliant
– 12 Mbit/s Full-Speed Mode
– 7 SW-configurable Endpoints, in addition to the bi-directional Control Endpoint 0
– 3 Configurations with 3 alternate settings and 4 interfaces supported
– Each non-Control Endpoint can be either Isochronous, Bulk or Interrupt
– Autonomous DMA Transfer by on-chip DMA for 8 USB endpoints
applications without USB, the input clock frequency can vary between 4 and 20 MHz
dependent on the CPU target clock frequency.
additional CPU clock slow-down mode with mode control for each peripheral
< 0.01%, 460.8 kBaud < 0.15 %, 691.2 kBaud < 0.04 %, 921.6 kBaud < 0.15 % ) @
36 MHz
compatibility up to 18 MBaud in SSC Master Mode and up to 9 MBaud in SSC Slave
Mode @ 36 MHz
12
2001-04-19
Overview
C161U