SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 31

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly functional C161U instruction set which
includes the following instruction classes:
• Arithmetic Instructions
• Logical Instructions
• Boolean Bit Manipulation Instructions
• Compare and Loop Control Instructions
• Shift and Rotate Instructions
• Prioritize Instruction
• Data Movement Instructions
• System Stack Instructions
• Jump and Call Instructions
• Return Instructions
• System Control Instructions
• Miscellaneous Instructions
Possible operand types are bits, bytes and words. Specific instruction support the
conversion (extension) of bytes to words. A variety of direct, indirect or immediate
addressing modes are provided to specify the required operands.
Programmable Multiple Priority Interrupt System
The following enhancements have been included to allow processing of a large number
of interrupt sources:
1. Peripheral Event Controller (PEC): This processor is used to off-load many interrupt
2. Multiple Priority Interrupt Controller: This controller allows all interrupts to be placed at
3. Multiple Register Banks: This feature allows the user to specify up to sixteen general
4. Interruptable Multiple Cycle Instructions: Reduced interrupt latency is provided by
Data Sheet
requests from the CPU. It avoids the overhead of entering and exiting interrupt or trap
routines by performing single-cycle interrupt-driven byte or word data transfers with
an optional increment of either the PEC source or the destination pointer. Just one
cycle is 'stolen' from the current CPU activity to perform a PEC service.
any specified priority. Interrupts may also be grouped, which provides the user with
the ability to prevent similar priority tasks from interrupting each other. For each of the
possible interrupt sources there is a separate control register, which contains an
interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. Once
having been accepted by the CPU, an interrupt service can only be interrupted by a
higher prioritized service request. For standard interrupt processing, each of the
possible interrupt sources has a dedicated vector location.
purpose registers located anywhere in the internal RAM. A single one-machine-cycle
instruction allows to switch register banks from one task to another.
allowing multiple-cycle instructions (multiply, divide) to be interruptable.
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Architectural Overview
2001-04-19
C161U