MC9S08DN32ACLH Freescale Semiconductor, MC9S08DN32ACLH Datasheet - Page 31

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MC9S08DN32ACLH

Manufacturer Part Number
MC9S08DN32ACLH
Description
IC MCU 32K FLASH 1.5K RAM 64LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets

Specifications of MC9S08DN32ACLH

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
S08DN
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
I2C, SCI, SPI
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 3
Modes of Operation
3.1
The operating modes of the MC9S08DN60 Series are described in this chapter. Entry into each mode, exit
from each mode, and functionality while in each of the modes are described.
3.2
3.3
This is the normal operating mode for the MC9S08DN60 Series. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset.
3.4
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user application program.
Freescale Semiconductor
Active background mode for code development
Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained
Stop modes — System clocks are stopped and voltage regulator is in standby
— Stop3 — All internal circuits are powered for fast recovery
— Stop2 — Partial power down of internal circuits; RAM content is retained
When the BKGD/MS pin is low at the rising edge of reset
When a BACKGROUND command is received through the BKGD/MS pin
When a BGND instruction is executed
When encountering a BDC breakpoint
When encountering a DBG breakpoint
Introduction
Features
Run Mode
Active Background Mode
MC9S08DN60 Series Data Sheet, Rev 3
31

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