MC9S08DN32ACLH Freescale Semiconductor, MC9S08DN32ACLH Datasheet - Page 16

• Manufacturer Part Number: MC9S08DN32ACLH
• Description: IC MCU 32K FLASH 1.5K RAM 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DN32ACLH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: S08DN
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C, SCI, SPI
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section Number
15.2 Signal Description ..........................................................................................................................264
15.3 Register Definition .........................................................................................................................268
15.4 Functional Description ...................................................................................................................274
15.5 Reset Overview ..............................................................................................................................279
15.6 Interrupts ........................................................................................................................................279
15.7 The Differences from TPM v2 to TPM v3.....................................................................................281
16.1 Introduction ....................................................................................................................................287
16.2 Background Debug Controller (BDC) ...........................................................................................288
16.3 On-Chip Debug System (DBG) .....................................................................................................297
16.4 Register Definition .........................................................................................................................301
16
15.1.3 Block Diagram ................................................................................................................262
15.2.1 Detailed Signal Descriptions ...........................................................................................264
15.3.1 TPM Status and Control Register (TPMxSC) ................................................................268
15.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................269
15.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................270
15.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................271
15.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................272
15.4.1 Counter ............................................................................................................................274
15.4.2 Channel Mode Selection .................................................................................................276
15.5.1 General ............................................................................................................................279
15.5.2 Description of Reset Operation .......................................................................................279
15.6.1 General ............................................................................................................................279
15.6.2 Description of Interrupt Operation ..................................................................................280
16.1.1 Forcing Active Background ............................................................................................287
16.1.2 Features ...........................................................................................................................288
16.2.1 BKGD Pin Description ...................................................................................................289
16.2.2 Communication Details ..................................................................................................290
16.2.3 BDC Commands .............................................................................................................294
16.2.4 BDC Hardware Breakpoint .............................................................................................296
16.3.1 Comparators A and B ......................................................................................................297
16.3.2 Bus Capture Information and FIFO Operation ...............................................................297
16.3.3 Change-of-Flow Information ..........................................................................................298
16.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................298
16.3.5 Trigger Modes .................................................................................................................299
16.3.6 Hardware Breakpoints ....................................................................................................301
16.4.1 BDC Registers and Control Bits .....................................................................................301
16.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................303
16.4.3 DBG Registers and Control Bits .....................................................................................304
MC9S08DN60 Series Data Sheet, Rev 3
Development Support
Chapter 16
Title
Freescale Semiconductor
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