MC9S08DN32ACLH Freescale Semiconductor, MC9S08DN32ACLH Datasheet - Page 308

• Manufacturer Part Number: MC9S08DN32ACLH
• Description: IC MCU 32K FLASH 1.5K RAM 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DN32ACLH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: S08DN
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C, SCI, SPI
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 16 Development Support
16.4.3.9
This is a read-only status register.
308
Reset
CNT[3:0]
ARMF
Field
3:0
AF
BF
W
7
6
5
R
AF
Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A
condition was met since arming.
0 Comparator A has not matched
1 Comparator A match
Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B
condition was met since arming.
0 Comparator B has not matched
1 Comparator B match
Arm Flag — While DBGEN = 1, this status bit is a read-only image of ARM in DBGC. This bit is set by writing 1
to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end of a debug run. A
debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A
debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC.
0 Debugger not armed
1 Debugger armed
FIFO Valid Count — These bits are cleared at the start of a debug run and indicate the number of words of valid
data in the FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO.
The external debug host is responsible for keeping track of the count as information is read out of the FIFO.
0000 Number of valid words in FIFO = No valid data
0001 Number of valid words in FIFO = 1
0010 Number of valid words in FIFO = 2
0011 Number of valid words in FIFO = 3
0100 Number of valid words in FIFO = 4
0101 Number of valid words in FIFO = 5
0110 Number of valid words in FIFO = 6
0111 Number of valid words in FIFO = 7
1000 Number of valid words in FIFO = 8
0
7
Debug Status Register (DBGS)
= Unimplemented or Reserved
BF
0
6
Table 16-6. DBGS Register Field Descriptions
Figure 16-9. Debug Status Register (DBGS)
ARMF
MC9S08DN60 Series Data Sheet, Rev 3
0
5
0
0
4
Description
CNT3
0
3
CNT2
0
2
Freescale Semiconductor
CNT1
1
0
CNT0
0
0