MC68376BAMAB20 Freescale Semiconductor, MC68376BAMAB20 Datasheet - Page 90

• Manufacturer Part Number: MC68376BAMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BAMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.3.3 External Bus Clock
5.3.4 Low-Power Operation
5-12
MOTOROLA
The state of the E-clock division bit (EDIV) in SYNCR determines clock rate for the E-
clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for M6800 devices
and peripherals. ECLK frequency can be set to system clock frequency divided by
eight or system clock frequency divided by sixteen. The clock is enabled by the CS10
field in chip-select pin assignment register 1 (CSPAR1). ECLK operation during low-
power stop is described in the following paragraph. Refer to 5.9 Chip-Selects for more
information about the external bus clock.
Low-power operation is initiated by the CPU32. To reduce power consumption selec-
tively, the CPU can set the STOP bits in each module configuration register. To mini-
mize overall microcontroller power consumption, the CPU can execute the LPSTOP
instruction, which causes the SIM to turn off the system clock.
When individual module STOP bits are set, clock signals inside each module are
turned off, but module registers are still accessible.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of
the current interrupt mask into the clock control logic. The SIM brings the MCU out of
low-power stop mode when one of the following exceptions occur:
Refer to 5.6.4.2 LPSTOP Broadcast Cycle and 4.8.2.1 Low-Power Stop (LPSTOP)
for more information.
During low-power stop mode, unless the system clock signal is supplied by an external
source and that source is removed, the SIM clock control logic and the SIM clock sig-
nal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the
RESET and IRQ pins are clocked by SIMCLK, and can be used to bring the processor
out of LPSTOP. Optionally, the SIM can also continue to generate the CLKOUT signal
while in low-power stop mode.
STSIM and STEXT bits in SYNCR determine clock operation during low-power stop
mode.
The flowchart shown in Figure 5-5 summarizes the effects of the STSIM and STEXT
bits when the MCU enters normal low power stop mode. Any clock in the off state is
held low. If the synthesizer VCO is turned off during low-power stop mode, there is a
PLL relock delay after the VCO is turned back on.
• RESET
• Trace
• SIM interrupt of higher priority than the stored interrupt mask
SYSTEM INTEGRATION MODULE
USER’S MANUAL
MC68336/376