C8051F321 Silicon Laboratories Inc, C8051F321 Datasheet - Page 73

• Manufacturer Part Number: C8051F321
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™
instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has
a superset of all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see descrip-
tion in
in
and 25 Port I/O (see description in
Section
control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram). The CIP-51 includes
the following features:
-
-
-
-
-
Section
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
25 Port I/O
Section
21), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or
CIP-51 MICROCONTROLLER
18), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space
19), an enhanced full-duplex UART (see description in
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
Section
PSW
PRGM. ADDRESS REG.
LOGIC
Figure 9.1. CIP-51 Block Diagram
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
14). The CIP-51 also includes on-chip debug hardware (see description in
TMP1
PIPELINE
ALU
TMP2
DATA BUS
DATA BUS
D8
D8
D8
Rev. 1.1
-
-
-
-
-
A16
D8
D8
D8
D8
B REGISTER
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
REGISTER
ADDRESS
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
MEMORY
SRAM
Section
SFR
BUS
17), an Enhanced SPI (see description
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
C8051F320/1
(Section
9.2.6),
73