C8051F321 Silicon Laboratories Inc, C8051F321 Datasheet - Page 230
C8051F321
Manufacturer Part Number
C8051F321
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheet
1.C8051F320R.pdf
(256 pages)
Specifications of C8051F321
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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C8051F320/1
19.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may oper-
ate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, or USB Start-of-Frame (SOF) capture mode. The
Timer 3 operation mode is defined by the T3SPLIT (TMR3CN.3) and T3SOF (TMR2CN.4) bits.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided
by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the internal oscillator drives the
system clock while Timer 3 (and/or the PCA) is clocked by an external precision oscillator. Note that the external
oscillator source divided by 8 is synchronized with the system clock.
19.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be clocked by
SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the 16-bit timer register
increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3 reload registers (TMR3RLH and
TM3RLL) is loaded into the Timer 3 register as shown in Figure 19.11, and the Timer 3 High Byte Overflow Flag
(TMR3CN.7) is set. If Timer 3 interrupts are enabled (if IE.5 is set), an interrupt will be generated on each Timer 3
overflow. Additionally, if Timer 3 interrupts are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be
generated each time the lower 8 bits (TMR3L) overflow from 0xFF to 0x00.
230
External Clock / 8
SYSCLK / 12
SYSCLK
T3XCLK
0
1
Figure 19.20. Timer 3 16-Bit Mode Block Diagram
M
T
3
H
M
T
3
L
0
1
CKCON
M
T
H
2
M
T
2
L
M
T
1
M
T
0
C
S
A
1
TR3
S
C
A
0
TCLK
Rev. 1.1
TMR3RLL TMR3RLH
TMR3L
TMR3H
Reload
To ADC
T3SPLIT
TF3LEN
T3XCLK
T3SOF
TF3H
TF3L
TR3
Interrupt
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