C8051F321 Silicon Laboratories Inc, C8051F321 Datasheet - Page 43

IC 8051 MCU 16K FLASH 28MLP

C8051F321

Manufacturer Part Number
C8051F321
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheet

Specifications of C8051F321

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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5.3.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is
continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in
low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks
(after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking
mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.3).
Tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track-
and-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements
described in
(AD0CM[2:0]=000, 001,010
Timer 1, Timer 3 Overflow
Write '1' to AD0BUSY,
Section “5.3.3. Settling Time Requirements” on page
(AD0CM[2:0]=100)
Timer 0, Timer 2,
Figure 5.3. 10-Bit ADC Track and Conversion Example Timing
SAR Clocks
SAR Clocks
SAR Clocks
AD0TM=1
AD0TM=0
011, 101)
AD0TM=1
AD0TM=0
CNVSTR
Low Power
or Convert
Low Power
or Convert
Track or
Convert
A. ADC0 Timing for External Trigger Source
Track or Convert
B. ADC0 Timing for Internal Trigger Source
1
1
Track
2
2
Track
3
3
4
4
Rev. 1.1
1
Convert
5
5
2
6
6
3
7
7
44.
4
8
Convert
8
Convert
Convert
5
9
9
6
10 11 12
10 11
7
8
C8051F320/1
9
13 14
10 11
Low Power Mode
Track
Low Power
Mode
Track
43

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