C8051F321 Silicon Laboratories Inc, C8051F321 Datasheet - Page 175

• Manufacturer Part Number: C8051F321
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Manage-
ment Bus Specification, version 1.1, and compatible with the I
system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data.
Data can be transferred at up to 1/10th of the system clock as a master or slave (this can be faster than allowed by the
SMBus specification, depending on the system clock used). A method of extending the clock-low duration is avail-
able to accommodate devices with different speed capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The
SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic,
and START/STOP control and generation. Three SFRs are associated with the SMBus: SMB0CF configures the
SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data register, used for both transmitting
and receiving SMBus data and slave addresses.
M
R
A
S
T
E
Interrupt
Request
SMBUS
M
X
O
D
E
T
SMB0CN
S
T
A
O
S
T
A
C
K
R
Q
O
A
R
B
S
T
L
A
C
K
S
I
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
IRQ Generation
SMBUS CONTROL LOGIC
M
E
N
S
B
N
H
I
Figure 16.1. SMBus Block Diagram
SMB0CF
B
U
S
Y
E
X
T
H
O
D
L
M
O
S
B
T
E
7
M
S
B
F
T
E
6
SMB0DAT
S
M
B
C
S
1
5
M
S
B
C
S
0
4
Data Path
3
Control
2
1
0
00
01
10
11
Rev. 1.1
Control
Control
SDA
SCL
2
C serial bus. Reads and writes to the interface by the
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
FILTER
FILTER
N
N
SDA
SCL
C8051F320/1
C
R
O
R
S
S
B
A
Port I/O
175