MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 572

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

QADC64E Enhanced Mode Operation
QADC64E to begin executing the CCWs in a queue or sub-queue. An “external trigger” is only one of the
possible “trigger events.”
A scan sequence may be initiated by the following:
The software also specifies whether the QADC64E is to perform a single pass through the queue or is to
scan continuously. When a single-scan mode is selected, the software selects the queue operating mode
and sets the single-scan enable bit. When a continuous-scan mode is selected, the queue remains active in
the selected queue operating mode after the QADC64E completes each queue scan sequence.
During queue execution, the QADC64E reads each CCW from the active queue and executes conversions
in three stages:
During initial sample, a buffered version of the selected input channel is connected to the sample capacitor
at the input of the sample buffer amplifier.
During the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges
the sample capacitor directly. Each CCW specifies a final input sample time of two or 16 QCLK cycles.
When an analog-to-digital conversion is complete, the result is written to the corresponding location in the
result word table. The QADC64E continues to sequentially execute each CCW in the queue until the end
of the queue is detected or a pause bit is found in a CCW.
When the pause bit is set in the current CCW, the QADC64E stops execution of the queue until a new
trigger event occurs. The pause status flag bit is set, which may cause an interrupt to notify the software
that the queue has reached the pause state. After the trigger event occurs, the paused state ends and the
QADC64E continues to execute each CCW in the queue until another pause is encountered or the end of
the queue is detected.
The following indicate the end-of-queue condition:
When any of the end-of-queue conditions is recognized, a queue completion flag is set, and if enabled, an
interrupt is issued to the software. The following situations prematurely terminate queue execution:
14-30
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A software command
Expiration of the periodic/interval timer
External trigger signal
External gated signal (queue 1 only)
Initial sample
Final sample
Resolution
The CCW channel field is programmed with 63 (0x3F) to specify the end of the queue
The end-of-queue 1 is implied by the beginning of queue 2, which is specified in the BQ2 field in
QACR2
The physical end of the queue RAM space defines the end of either queue
Since queue 1 is higher in priority than queue 2, when a trigger event occurs on queue 1 during
queue 2 execution, the execution of queue 2 is suspended by aborting the execution of the CCW in
progress, and the queue 1 execution begins. When queue 1 execution is completed, queue 2
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor