MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 7
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MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
154
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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2.7.5
2.8
2.8.1
2.8.2
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
4.1
4.2
4.3
4.4
4.4.1
4.5
4.5.1
4.6
4.7
4.8
4.8.1
4.8.2
4.9
4.9.1
4.9.1.1
4.9.1.2
4.9.1.3
4.9.2
4.9.3
4.9.3.1
4.9.3.2
4.9.3.3
4.9.3.4
4.9.4
Paragraph
Number
Exception Processing Overview ....................................................................... 2-47
Overview............................................................................................................. 3-1
MAC Instruction Execution Timings.................................................................. 3-5
Interactions between Local Memory Modules ................................................... 4-1
SRAM Overview ................................................................................................ 4-1
SRAM Operation ................................................................................................ 4-2
SRAM Programming Model............................................................................... 4-3
SRAM Initialization............................................................................................ 4-4
Power Management ............................................................................................ 4-6
Cache Overview.................................................................................................. 4-6
Cache Organization............................................................................................. 4-7
Cache Operation................................................................................................ 4-11
Branch Instruction Execution Times ............................................................ 2-46
Exception Stack Frame Definition................................................................ 2-49
Processor Exceptions .................................................................................... 2-50
MAC Programming Model............................................................................. 3-2
General Operation........................................................................................... 3-3
MAC Instruction Set Summary ...................................................................... 3-4
Data Representation........................................................................................ 3-4
SRAM Base Address Register (RAMBAR)................................................... 4-3
SRAM Initialization Code .............................................................................. 4-5
Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified............. 4-8
The Cache at Start-Up..................................................................................... 4-9
Caching Modes ............................................................................................. 4-13
Cache-Inhibited Accesses ............................................................................. 4-14
Cache Protocol.............................................................................................. 4-15
Cache Coherency ......................................................................................... 4-17
Cacheable Accesses .................................................................................. 4-13
Write-Through Mode ............................................................................... 4-14
Copyback Mode ....................................................................................... 4-14
Read Miss ................................................................................................. 4-15
Write Miss ............................................................................................... 4-16
Read Hit .................................................................................................... 4-16
Write Hit .................................................................................................. 4-16
Hardware Multiply/Accumulate (MAC) Unit
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
CONTENTS
Local Memory
Chapter 3
Chapter 4
Contents
Title
Number
Page
vii
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