MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 131
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MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
154
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor, Inc.
Real-Time Trace Support
Figure 5-2 shows PSTCLK timing with respect to PST and DDATA.
PSTCLK
PST
DDATA
or
Figure 5-2. PSTCLK Timing
5.3 Real-Time Trace Support
Real-time trace, which defines the dynamic execution path, is a fundamental debug
function. The ColdFire solution is to include a parallel output port providing encoded
processor status and data to an external development system. This port is partitioned into
two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and
the other allows operand data to be displayed (debug data, DDATA). The processor status
may not be related to the current bus transfer.
External development systems can use PST outputs with an external image of the program
to completely track the dynamic execution path. This tracking is complicated by any
change in flow, especially when branch target address calculation is based on the contents
of a program-visible register (variant addressing). DDATA outputs can be configured to
display the target address of such instructions in sequential nibble increments across
multiple processor clock cycles, as described in Section 5.3.1, “Begin Execution of Taken
Branch (PST = 0x5).” Two 32-bit storage elements form a FIFO buffer connecting the
processor’s high-speed local bus to the external development system through PST[3:0] and
DDATA[3:0]. The buffer captures branch target addresses and certain data values for
eventual display on the DDATA port, one nibble at a time starting with the lsb.
Execution speed is affected only when both storage elements contain valid data to be
dumped to the DDATA port. The core stalls until one FIFO entry is available.
Table 5-2 shows the encoding of these signals.
Chapter 5. Debug Support
5-3
For More Information On This Product,
Go to: www.freescale.com
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