MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 235
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MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
154
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
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Chapter 11
Synchronous/Asynchronous DRAM
Controller Module
This chapter describes configuration and operation of the synchronous/asynchronous
DRAM controller component of the system integration module (SIM). It begins with a
general description and brief glossary, and includes a description of signals involved in
DRAM operations. The remainder of the chapter consists of the two following parts:
11.1 Overview
The DRAM controller module provides glueless integration of DRAM with the ColdFire
product. The key features of the DRAM controller include the following:
• Section 11.3, “Asynchronous Operation,” describes the programming model and
• Section 11.4, “Synchronous Operation,” describes the programming model and
• Support for two independent blocks of DRAM
• Interface to standard synchronous/asynchronous dynamic random access memory
• Programmable SRAS, SCAS, and refresh timing
• Support for page mode
• Support for 8-, 16-, and 32-bit wide DRAM blocks
• Support for synchronous and asynchronous DRAMs, including EDO DRAM,
signal timing for the four basic asynchronous modes.
— Non-page mode
— Burst page mode
— Continuous page mode
— Extended data-out mode
signal timing, as well as the command set required for synchronous operations. This
section also includes extensive examples the designer can follow to better
understand how to configure the DRAM controller for synchronous operations.
(ADRAM/SDRAM) components
SDRAM, and fast page mode
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
11-1
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