MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 32

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Organization
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• Part II, “System Integration Module (SIM),” describes the system integration
— Chapter 4, “Local Memory.” This chapter describes the MCF5307
— Chapter 5, “Debug Support,” describes the Revision C enhanced hardware debug
module, which provides overall control of the bus and serves as the interface
between the ColdFire core processor complex and internal peripheral devices. It
includes a general description of the SIM and individual chapters that describe
components of the SIM, such as the phase-lock loop (PLL) timing source, interrupt
controller for peripherals, configuration and operation of chip selects, and the
SDRAM controller.
— Chapter 6, “SIM Overview,” describes the SIM programming model, bus
— Chapter 7, “Phase-Locked Loop (PLL),” describes configuration and operation
— Chapter 8, “I
— Chapter 9, “Interrupt Controller,” describes operation of the interrupt controller
— Chapter 10, “Chip-Select Module,” describes the MCF5307 chip-select
— Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,”
implementation of the ColdFire V3 local memory specification. It consists of the
two following major sections.
– Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM
– Section 4.7, “Cache Overview,” describes the MCF5307 cache
support in the MCF5307. This revision of the ColdFire debug architecture
encompasses earlier revisions.
arbitration, and system-protection functions for the MCF5307.
of the PLL module. It describes in detail the registers and signals that support the
PLL implementation.
protocol, clock synchronization, and the registers in the I
It also provides extensive programming examples.
portion of the SIM. Includes descriptions of the registers in the interrupt
controller memory map and the interrupt priority scheme.
implementation, including the operation and programming model, which
includes the chip-select address, mask, and control registers.
describes configuration and operation of the synchronous/asynchronous DRAM
controller component of the SIM. It begins with a general description and brief
glossary, and includes a description of signals involved in DRAM operations.
The remainder of the chapter is divided between descriptions of asynchronous
and synchronous operations.
(SRAM) implementation. It covers general operations, configuration, and
initialization. It also provides information and examples showing how to
minimize power consumption when using the SRAM.
implementation, including organization, configuration, and coherency. It
describes cache operations and how the cache interacts with other memory
structures.
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Freescale Semiconductor, Inc.
C Module,” describes the MCF5307 I
For More Information On This Product,
Go to: www.freescale.com
MCF5307 User’s Manual
2
C module, including I
2
C programing model.
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C