MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 467
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MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
154
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1
0x3CC
0x3CC
MBAR
Offset
0x3C0
0x3C4
0x3C8
0x3D0
0x3D4
On the 0H55J and 1H55J revisions of the MCF5307, the byte count register of the DMA channels can
accommodate only 16 bits. However, on the newest revision of the MCF5307, an expanded 24-bit byte count
range provides greater flexibility. For this reason, the position of the byte count register (BCR) in the memory
map depends on whether a 16- or 24-bit byte counter is chosen. The selection is made by programming
MPARK[BCR24BIT] in the SIM module.
In the new MCF5307, the 24-bit byte count can be selected by setting BCR24BIT = 1, making DCR[AT]
available. The AT bit selects whether the DMA channels assert an acknowledge during the entire transfer or
only at the final transfer of a DMA transaction.
New applications should take advantage of the full range of the 24-bit byte counter, including the AT bit. The
16-bit byte count option (BCR24BIT = 0) is kept to retain compatibility with older revisions of the MCF5307.
0x394
DMA status register 3
DMA interrupt vector
DMA interrupt vector
register 2 (DIVR2)
register 3 (DIVR3)
(DSR3) [p. 12-10]
Byte count register 3 (BCR24BIT = 0)
Reserved
[p. 12-11]
[p. 12-11]
[31:24]
Table A-10. DMA Controller Registers (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
Appendix A. List of Memory Maps
Destination address register 3 (DAR3) [p. 12-7]
Source address register 3 (SAR3) [p. 12-6]
Go to: www.freescale.com
DMA control register 3 (DCR3) [p. 12-8]
[23:16]
Byte count register 3 (BCR24BIT = 1)
1
Reserved
Reserved
Reserved
[15:8]
Reserved
1
(BCR3) [p. 12-7]
[7:0]
A-9
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