MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 82
MC68332ACFC25
Manufacturer Part Number
MC68332ACFC25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68332ACFC25
Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Quantity
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Part Number:
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4.6.5 Pin State During Reset
4.6.5.1 Reset States of SIM Pins
4-42
It is important to keep the distinction between pin function and pin electrical state clear.
Although control register values and mode select inputs determine pin function, a pin
driver can be active, inactive or in high-impedance state while reset occurs. During
power-up reset, pin state is subject to the constraints discussed in 4.6.7 Power-On
Reset.
Generally, while RESET is asserted, SIM pins either go to an inactive high-impedance
state or are driven to their inactive states. After RESET is released, mode selection
occurs, and reset exception processing begins. Pins configured as inputs during reset
become active high-impedance loads after RESET is released. Inputs must be driven
to the desired active state. Pull-up or pull-down circuitry may be necessary. Pins con-
figured as outputs begin to function after RESET is released. Table 4-18 is a summary
of SIM pin states during reset.
Module
CPU32
QSM
GPT
Pins that are not used should either be configured as outputs, or (if
configured as inputs) pulled to the appropriate inactive state. This de-
creases additional I
ply level.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-17 Module Pin Functions
SYSTEM INTEGRATION MODULE
DD
Go to: www.freescale.com
PQS[6:4]/PCS[3:1]
PGP[6:3]/OC[4:1]
PGP[2:0]/IC[3:1]
PQS3/PCS0/SS
PGP7/IC4/OC5
Pin Mnemonic
PWMA, PWMB
BKPT/DSCLK
caused by digital inputs floating near mid-sup-
DSI/IFETCH
PQS1/MOSI
PQS0/MISO
DSO/IPIPE
PQS7/TXD
PQS2/SCK
PCLK
RXD
PAI
NOTE
Discrete Output
BKPT/DSCLK
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
DSI/IFETCH
DSO/IPIPE
Function
RXD
USER’S MANUAL
MC68332
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