MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 66
MC68332ACFC25
Manufacturer Part Number
MC68332ACFC25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68332ACFC25
Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number:
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4.5.3 Fast Termination Cycles
4-26
When an external device has a fast access time, the chip-select circuit fast-termination
option can provide a two-cycle external bus transfer. Because the chip-select circuits
are driven from the system clock, the bus cycle termination is inherently synchronized
with the system clock.
If multiple chip selects are to be used to select the same device that can support fast
termination, and match conditions can occur simultaneously, program the DSACK
field in each associated chip-select option register for fast termination. Alternately, pro-
gram one DSACK field for fast termination and the remaining DSACK fields for exter-
nal termination.
Fast termination cycles use internal handshaking signals generated by the chip-select
logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals.
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
1) NEGATE DS AND AS
2) REMOVE DATA FROM DATA BUS
1) SET R/W TO WRITE
ASSERT DS AND WAIT FOR DSACK (S3)
TERMINATE OUTPUT TRANSFER (S5)
PLACE DATA ON DATA[15:0] (S2)
ADDRESS DEVICE (S0)
OPTIONAL STATE (S4)
START NEXT CYCLE
ASSERT AS (S1)
NO CHANGE
MCU
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 4-10 Write Cycle Flowchart
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
1) DECODE ADDRESS
2) LATCH DATA FROM DATA BUS
3) ASSERT DSACK SIGNALS
1) NEGATE DSACK
ACCEPT DATA (S2 + S3)
TERMINATE CYCLE
PERIPHERAL
USER’S MANUAL
WR CYC FLOW
MC68332
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