MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 72
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MC68332ACFC25
Manufacturer Part Number
MC68332ACFC25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68332ACFC25
Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68332ACFC25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68332ACFC25
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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4-32
Retry Termination
Table 4-14 shows various combinations of control signal sequences and the resulting
bus cycle terminations.
NOTES:
To properly control termination of a bus cycle for a retry or a bus error condition,
DSACK, BERR, and HALT must be asserted and negated with the rising edge of the
MCU clock. This ensures that when two signals are asserted simultaneously, the re-
quired setup time and hold time for both of them are met for the same falling edge of
the MCU clock. (Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for timing
requirements.) External circuitry that provides these signals must be designed with
these constraints in mind, or else the internal bus monitor must be used.
DSACK, BERR, and HALT may be negated after AS is negated.
Number
Case
N
A
NA = Signal is not asserted in this state
X
S
HALT and BERR are asserted in lieu of, at the same time as, or before DSACK or
after DSACK; BERR is negated at the same time or after DSACK; HALT may be
negated at the same time or after BERR.
1
2
3
4
5
6
= The number of current even bus state (S2, S4, etc.).
= Signal is asserted in this bus state.
= Don't care.
= Signal was asserted in previous state and remains asserted in this state.
If DSACK or BERR remain asserted into S2 of the next bus cycle,
that cycle may be terminated prematurely.
Table 4-14 DSACK, BERR, and HALT Assertion Results
Control Signal
DSACK
DSACK
DSACK
DSACK
DSACK
DSACK
BERR
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
HALT
Freescale Semiconductor, Inc.
For More Information On This Product,
Asserted on Rising
SYSTEM INTEGRATION MODULE
NA/A
NA/A
Edge of State
A/S
A/S
NA
NA
NA
NA
NA
NA
NA
N
A
A
A
A
A
A
A
Go to: www.freescale.com
N + 2
NA
NA
NA
S
X
S
S
X
S
X
X
S
X
S
S
X
A
A
WARNING
Normal termination.
Halt termination: normal cycle terminate and halt.
Continue when HALT is negated.
Bus error termination: terminate and take bus error
exception, possibly deferred.
Bus error termination: terminate and take bus error
exception, possibly deferred.
Retry termination: terminate and retry when HALT is
negated.
Retry termination: terminate and retry when HALT is
negated.
Result
USER’S MANUAL
MC68332
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