MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 44

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.2.3 Show Internal Cycles
4.2.4 Factory Test Mode
4.2.5 Register Access
4.2.6 Reset Status
4-4
terrupt request is acknowledged, even when there is only a single request pending.
For an interrupt to be serviced, the appropriate IARB field must have a non-zero value.
If an interrupt request from a module with an IARB field value of %0000 is recognized,
the CPU32 processes a spurious interrupt exception.
Because the SIM routes external interrupt requests to the CPU32, the SIM IARB field
value is used for arbitration between internal and external interrupts of the same pri-
ority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all
other modules is %0000, which prevents SIM interrupts from being discarded during
initialization. Refer to 4.7 Interrupts for a discussion of interrupt arbitration.
A show cycle allows internal bus transfers to be monitored externally. The SHEN field
in the SIMCR determines what the external bus interface does during internal transfer
operations. Table 4-1 shows whether data is driven externally, and whether external
bus arbitration can occur. Refer to 4.5.6.2 Show Cycles for more information.
The internal IMB can serve as slave to an external master for direct module testing.
This test mode is reserved for factory test. Slave mode is enabled by holding DATA11
low during reset. The slave enabled (SLVEN) bit is a read-only bit that shows the reset
state of DATA11.
The CPU32 can operate at either of two privilege levels. Supervisor level is more priv-
ileged than user level — all instructions and system resources are available at super-
visor level, but access is restricted at user level. Effective use of privilege level can
protect system resources from uncontrolled access. The state of the S bit in the CPU
status register determines access level, and whether the user or supervisor stack
pointer is used for stacking operations. The SUPV bit places SIM global registers in
either supervisor or user data space. When SUPV = 0, registers with controlled access
are accessible from either the user or supervisor privilege level; when SUPV = 1, reg-
isters with controlled access are restricted to supervisor access only.
The reset status register (RSR) latches internal MCU status during reset. Refer to
4.6.9 Reset Status Register for more information.
SHEN
00
01
10
11
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Table 4-1 Show Cycle Enable Bits
SYSTEM INTEGRATION MODULE
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
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MC68332