MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 126
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MC68332ACFC25
Manufacturer Part Number
MC68332ACFC25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68332ACFC25
Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68332ACFC25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68332ACFC25
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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6.3 Queued Serial Peripheral Interface
6-4
NOTES:
the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI.
PQSPAR does not affect operation of the SCI.
The port QS data direction register (DDRQS) determines whether pins are inputs or
outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the
pin an output. DDRQS affects both QSPI function and I/O function. DDQS1 deter-
mines the direction of the TXD pin only when the SCI transmitter is disabled. When the
SCI transmitter is enabled, the TXD pin is an output. PQSPAR and DDRQS are 8-bit
registers located at the same word address. Table 6-1 is a summary of QSM pin func-
tions.
The port QS data register (PORTQS) latches I/O data. Writes to PORTQS drive pins
defined as outputs. PORTQS reads return data present on the pins when the read is
made. To avoid driving undefined data, first write PORTQS, then configure DDRQS.
The queued serial peripheral interface (QSPI) communicates with external devices
through a synchronous serial bus. The QSPI is fully compatible with SPI systems
found on other Freescale products, but has enhanced capabilities. The QSPI can per-
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes the SPI
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 set), in which case it becomes
serial clock SCK.
SCI serial output TXD and DDRQS has no effect.
PCS0/SS
QSM Pin
PCS[3:1]
MISO
MOSI
SCK
TXD
RXD
1
2
Freescale Semiconductor, Inc.
Transmit
Receive
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
For More Information On This Product,
Table 6-1 QSM Pin Function
QUEUED SERIAL MODULE
Go to: www.freescale.com
DDRQS Bit
DDQS[4:6]
DDQS0
DDQS1
DDQS2
DDQS3
DDQS7
None
Bit State
NA
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Serial Data Output from QSPI
Serial Data Output from QSPI
Assertion Causes Mode Fault
Disables Chip-Select Output
Serial Data Output from SCI
Serial Data Input to QSPI
Serial Data Input to QSPI
Clock Output from QSPI
QSPI Slave Select Input
Serial Data Input to SCI
Disables Clock Output
Disables Data Output
Disables Data Output
Disables Select Input
Disables Clock Input
Disables Data Input
Disables Data Input
Clock Input to QSPI
Chip-Select Output
Chip-Select Output
Pin Function
Inactive
Inactive
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