MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 232
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MC68332ACFC25
Manufacturer Part Number
MC68332ACFC25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68332ACFC25
Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68332ACFC25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68332ACFC25
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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D.4 Queued Serial Module
D.4.1 QSMCR — QSM Configuration Register
STOP — Stop Enable
D-18
STOP
15
0
Table D-4 is the QSM address map. The column labeled “Access” indicates the privi-
lege level at which the CPU must be operating to access the register. A designation of
“S” indicates that supervisor access is required: a designation of “S/U” indicates that
the register can be programmed to the desired privilege level.
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
QSMCR bits enable stop and freeze modes, and determine the arbitration priority of
QSM interrupt requests.
When STOP is set, the QSM enters low-power stop mode. System clock input to the
module is disabled. While STOP is asserted, only QSMCR reads are guaranteed to be
valid, but writes to QSPI RAM or any register are guaranteed valid. STOP is set during
RESET:
QUEUE RAM
QUEUE RAM
QUEUE RAM
Access
0 = Normal QSM clock operation
1 = QSM clock operation stopped
FRZ1
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
14
S
S
S
0
FRZ0
13
0
12
0
0
$YFFC20–
$YFFD00–
$YFFD20–
$YFFD40–
$YFFC0C
$YFFC1C
$YFFC00
$YFFC02
$YFFC04
$YFFC06
$YFFC08
$YFFC0A
$YFFC0E
$YFFC10
$YFFC12
$YFFC14
$YFFC16
$YFFC18
$YFFC1A
$YFFC1E
$YFFCFF
$YFFD1F
$YFFD3F
$YFFD4F
Address
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
0
Table D-4 QSM Address Map
15 8
10
0
0
PQS PIN ASSIGNMENT (PQSPAR)
QSM INTERRUPT LEVEL (QILR)
Go to: www.freescale.com
REGISTER SUMMARY
SPI CONTROL 3 (SPCR3)
9
0
0
NOT USED
8
0
0
QSM MODULE CONFIGURATION (QSMCR)
SUPV
7
1
COMMAND RAM (CR[0:F])
SCI CONTROL 0 (SCCR0)
SCI CONTROL 1 (SCCR1)
SPI CONTROL 0 (SPCR0)
SPI CONTROL 1 (SPCR1)
SPI CONTROL 2 (SPCR2)
TRANSMIT RAM (TR[0:F])
RECEIVE RAM (RR[0:F])
SCI STATUS (SCSR)
QSM TEST (QTEST)
SCI DATA (SCDR)
6
0
0
NOT USED
NOT USED
NOT USED
NOT USED
5
0
0
7 0
QSM INTERRUPT VECTOR (QIVR)
PQS DATA DIRECTION (DDRQS)
4
0
0
PQS DATA (PORTQS)
SPI STATUS (SPSR)
3
0
USER’S MANUAL
0
IARB
$YFFC00
0
MC68332
0
0
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