ST7FMC2R7T6TR STMicroelectronics, ST7FMC2R7T6TR Datasheet - Page 69

• Manufacturer Part Number: ST7FMC2R7T6TR
• Description: IC MCU 8BIT 32K FLASH 64-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R7T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ON-CHIP PERIPHERALS (Cont’d)
Independent PWM signal generation
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during Halt mode.
Each PWMx output signal can be selected inde-
pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as out-
put push-pull alternate function.
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARTARR register value.
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
Figure 40. PWM Auto-reload Timer Function
Figure 41. PWM Signal from 0% to 100% Duty Cycle
f
AUTO-RELOAD
PWM
DUTY CYCLE
(PWMDCRx)
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
REGISTER
REGISTER
(ARTARR)
= f
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
COUNTER
f
COUNTER
COUNTER
255
000
/ (256 - ARTARR)
FDh
FEh
ARTARR=FDh
FFh
FDh
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARTARR reg-
ister.
The maximum available resolution for the PWMx
duty cycle is:
Note: To get the maximum resolution (1/256), the
ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by
changing the polarity.
Resolution = 1 / (256 - ARTARR)
FEh
FFh
ST7MC1xx/ST7MC2xx
FDh
FEh
69/309
t
t
1