ST7FMC2R7T6TR STMicroelectronics, ST7FMC2R7T6TR Datasheet - Page 150

• Manufacturer Part Number: ST7FMC2R7T6TR
• Description: IC MCU 8BIT 32K FLASH 64-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R7T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.3 D Event detection
In sensorless mode, the D Window Filter becomes
active after each C event. It blanks out the D event
during the time window defined by the DWF[3:0]
bits in the MDFR register (see
value is 200µs.
This Window Filter becomes active after both
hardware and software C events.
The D Event Filter becomes active after the D Win-
dow Filter. It counts the number of consecutive D
events up to a limit defined by the DEF[3:0] bits in
the MDFR register. The reset value is 1. The D bit
is set when the counter limit is reached.
Sampling is done at a selectable frequency
(f
The D event filter is active only for a hardware D
event (D
to 1.
Figure 79.
150/309
1
SCF
), see
Reset counter
H
). For a simulated (D
D Window and Event Filter Flowchart
Table
No
No
No
Increment counter
Blanking Window
Counter=Limit?
82.
Set the D bit
Sampling
Yes
End of
Event
C
D
?
?
Yes
No
Table
S
) event, it is forced
WINDOW
26). The reset
FILTER
FILTER
EVENT
Yes
Limit=1?
Yes
Note: Times are indicated for 4 MHz f
Table 27. D Event filter Setting
DWF3 DWF2 DWF1 DWF0
DEF3 DEF2 DEF1 DEF0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C to D window fil-
ter in Sensorless
D event Limit
Mode (SR=0)
100 µs
120 µs
140 µs
160 µs
180 µs
200 µs
10 µs
15 µs
20 µs
25 µs
30 µs
35 µs
40 µs
60 µs
80 µs
5 µs
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PERIPH
SR=1
SR=1