ST7FMC2R7T6TR STMicroelectronics, ST7FMC2R7T6TR Datasheet - Page 212

• Manufacturer Part Number: ST7FMC2R7T6TR
• Description: IC MCU 8BIT 32K FLASH 64-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R7T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
CONTROL REGISTER B (MCRB)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7= Reserved, must be kept at reset value.
Bit 6= CPB*: Compare Bit for Zero-crossing detec-
tion.
0: Zero crossing detection on falling edge
1: Zero crossing detection on rising edge
Bit 5= HDM*: Hardware Demagnetization event
Mask bit
0: Hardware Demagnetization disabled
1: Hardware Demagnetization enabled
Bit 4= SDM*: Simulated Demagnetization event
Mask bit
0: Simulated Demagnetization disabled
1: Simulated Demagnetization enabled
Bit 3 = OCV: Over Current Handling in Voltage
mode
0: Over Current protection is OFF
1:Over current protection is ON
This bit acts as follows
Table 60. Over current handling
212/309
1
CLIM bit CLI bit OCV bit
7
0
0
0
1
1
1
CPB*
6
0
1
0
1
1
HDM* SDM*
5
0
1
x
x
x
4
state (MOE reset)
Current loop effect
Current loop effect
PWM is put off as
PWM is put off as
All MCOx outputs
Normal running
Normal running
OCV
are put in reset
Output effect
3
mode
mode
OS2*
2
OS1
1
1)
Interrupt
Yes
Yes
OS0
No
No
No
0
Note 1: This feature is also available when using
the three PWM outputs (PCN bit=1 in the MDTG
register), providing that the VOC1bit = 0 (MCRA
register). See
Bits 2:0 = OS2*, OS[1:0]: Operating output mode
Selection bits
Refer to the Step behaviour diagrams
Figure
sorless mode,” on page 212.
These bits are used to define the various PWM
output configurations.
Note: OS2 is the only preload bit.
Table 61. Step Behaviour/ sensorless mode
Note: For more details, see Step behaviour dia-
grams
* Preload bits, new value taken into account at the
next C event. A C event is generated at each write
to MPHST in Direct Access mode.
OS2
bit
0
1
PWM after
Channels
Channels
before D
On High
On Low
(Figure 109
110) and Table 61, “Step Behaviour/ sen-
C and
section 10.6.8.2 on page 186
OS1
bit
0
1
0
1
and
PWM after
Channels
Channels
Channels
Channels
before Z
On High
On High
On Low
On Low
Figure
D and
110).
OS0
0
1
0
1
0
1
0
1
(Figure
before next
PWM after
channels
channels
channels
channels
channels
channels
channels
channels
On high
On high
On high
On high
On low
On low
On low
On low
Z and
C
109,