P89CV51RC2FBC,557 NXP Semiconductors, P89CV51RC2FBC,557 Datasheet - Page 66

• Manufacturer Part Number: P89CV51RC2FBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89CV51RC2FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89CV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4255; 935284104557; P89CV51RC2FBC

NXP Semiconductors
Table 58.
P89CV51RB2_RC2_RD2_3
Product data sheet
Symbol Parameter
f
T
t
t
t
t
t
t
t
t
t
t
t
t
SPI
SPILEAD
SPILAG
SPICLKH
SPICLKL
SPIDSU
SPIDH
SPIA
SPIDIS
SPIDV
SPIOH
SPIR
SPIF
Fig 33. Shift register mode timing waveforms
SPICYC
SPI operating frequency
SPI cycle time
SPI enable lead time
SPI enable lag time
SPICLK HIGH time
SPICLK LOW time
SPI data set-up time
SPI data hold time
SPI access time
SPI disable time
SPI enable to output data
valid time
SPI output data hold time
SPI rise time
SPI fall time
write to SBUF
output data
SPI interface timing
instruction
input data
clear RI
clock
ALE
t
t
QVXH
XHDV
valid
T
0
XLXL
Conditions
see
see
see
see
see
master or slave;
see
master or slave;
see
see
see
see
see
see
see
t
SPI outputs (SPICLK, MOSI,
MISO)
SPI inputs (SPICLK, MOSI,
MISO, SS)
SPI outputs (SPICLK, MOSI,
MISO)
SPI inputs (SPICLK, MOSI,
MISO, SS)
XHDX
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
t
valid
XHQX
1
Rev. 03 — 25 August 2009
34, 35, 36,
36,
36,
34, 35, 36,
34, 35, 36,
34, 35, 36,
34, 35, 36,
36,
36,
34, 35, 36,
34, 35, 36,
34, 35, 36,
34, 35, 36,
valid
37
37
37
37
2
37
37
37
37
37
37
37
37
37
valid
3
P89CV51RB2/RC2/RD2
valid
4
4T
2T
2T
Min
250
250
100
100
Variable clock
cy(clk)
cy(clk)
cy(clk)
0
0
0
0
-
-
-
-
-
valid
5
T
cy(clk)
2000
2000
Max
160
111
100
100
80
80C51 with 1 kB RAM, SPI
valid
-
-
-
-
-
-
-
-
6
/ 4
f
osc
Min
222
250
250
111
111
100
100
valid
© NXP B.V. 2009. All rights reserved.
set TI
0
0
0
set RI
-
-
-
-
-
-
7
002aaa552
= 18 MHz
2000
2000
Max
160
111
100
100
80
10
-
-
-
-
-
-
-
-
66 of 76
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns