P89CV51RC2FBC,557 NXP Semiconductors, P89CV51RC2FBC,557 Datasheet - Page 53

• Manufacturer Part Number: P89CV51RC2FBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89CV51RC2FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89CV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4255; 935284104557; P89CV51RC2FBC

NXP Semiconductors
Table 41.
P89CV51RB2_RC2_RD2_3
Product data sheet
Description
External
Interrupt 0
T0
External
Interrupt 1
T1
UART
SPI
PCA
T2
Interrupt polling sequence
6.10 Security bits
6.11 Interrupt priority and polling sequence
Interrupt flag
IE0
TF0
IE1
TF1
TI/RI
SPIF
CF/CCFn
TF2, EXF2
The security bits protect against software piracy and prevent the contents of the flash from
being read by unauthorized parties in Parallel programmer mode and ISP mode. Since the
end application might need to erase pages and read from the code memory, the security
bits have no effect in IAP mode. However, the security bits’ programmed/erased state may
be read using IAP function calls allowing the end-user code to limit access, if desired. The
security bits and their effects are shown in
Note: On this device, MOVC instructions executed from external code memory are
prevented from fetching code bytes from internal code memory.
Table 40.
The device supports eight interrupt sources under a four-level priority scheme.
summarizes the polling sequence of the supported interrupts. Note that the SPI serial
interface and the UART share the same interrupt vector; see
Security bit
1
2
3
Vector address Interrupt
0003H
000BH
0013H
001BH
0023H
0023H
0033H
003BH
Security bit functions
Description
Write protect. When programmed, prohibits further erasing or
programming, except to program other security bits or a chip erase.
Read protect. When programmed, inhibits reading of user code memory.
External execution inhibit. When programmed, prevents any execution of
instructions from external code memory.
Rev. 03 — 25 August 2009
enable
EX0
ET0
EX1
ET1
ES
ES
EC
ET2
P89CV51RB2/RC2/RD2
Interrupt
priority
PX0/PX0H
PT0/PT0H
PX1/PX1H
PT1/PT1H
PS/PSH
PS/PSH
PPC/PPCH
PT2/PT2H
Table
40.
Service
priority
1 (highest)
2
3
4
5
5
7
6
Figure
80C51 with 1 kB RAM, SPI
25.
© NXP B.V. 2009. All rights reserved.
Wake-up
Power-down
yes
no
yes
no
no
no
no
no
Table 41
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