P89CV51RC2FBC,557 NXP Semiconductors, P89CV51RC2FBC,557 Datasheet - Page 39

• Manufacturer Part Number: P89CV51RC2FBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89CV51RC2FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89CV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4255; 935284104557; P89CV51RC2FBC

NXP Semiconductors
P89CV51RB2_RC2_RD2_3
Product data sheet
6.6.9 Automatic address recognition
SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop
bit, although it is preferable to use the Framing Error flag (FE). When the UART receives
data in Mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop
bit is received.
Automatic address recognition is a feature which allows the UART to recognize certain
addresses in the serial bit stream by using hardware to make the comparisons. This
feature saves a great deal of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This feature is enabled for
the UART by setting the SM2 bit in SCON. In the 9-bit UART modes, Mode 2 and Mode 3,
the Receive Interrupt flag (RI) will be automatically set when the received byte contains
either the ‘given’ address or the ‘broadcast’ address. The 9-bit mode requires that the 9th
information bit is a 1 to indicate that the received information is an address and not data.
Using the automatic address recognition feature allows a master to selectively
communicate with one or more slaves by invoking the given slave address or addresses.
All of the slaves may be contacted by using the broadcast address. Two special function
registers are used to define the slave’s address, SADDR, and the address mask, SADEN.
SADEN is used to define which bits in the SADDR are to be used and which bits are don’t
care. The SADEN mask can be logically ANDed with the SADDR to create the given
address which the master will use for addressing each of the slaves. Use of the given
address allows multiple slaves to be recognized while excluding others.
This device uses the methods presented in
address has been received or not.
Fig 15. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when
multiprocessor communications is enabled
rx_byte(7)
rx_byte(0)
saden(7)
saden(0)
saddr(7)
saddr(0)
saddr(7)
saddr(0)
logic used by UART to detect 'given address' in received data
logic used by UART to detect 'given address' in received data
Rev. 03 — 25 August 2009
rx_byte(7)
rx_byte(0)
saden(7)
saden(0)
.
.
.
.
.
.
P89CV51RB2/RC2/RD2
Figure 15
given_address_match
broadcast_address_match
to determine if a given or broadcast
80C51 with 1 kB RAM, SPI
002aaa527
© NXP B.V. 2009. All rights reserved.
39 of 76