AT91SAM7S512-MU-999 Atmel, AT91SAM7S512-MU-999 Datasheet - Page 737
![IC MCU ARM7 512KB FLASH 64-VQFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT91SAM7S512-MU-999
Manufacturer Part Number
AT91SAM7S512-MU-999
Description
IC MCU ARM7 512KB FLASH 64-VQFN
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S512-MU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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40.21 AT91SAM7S32 Errata - Revision B Parts
40.21.1
40.21.1.1
40.21.1.2
40.21.1.3
40.21.1.4
40.21.1.5
40.21.1.6
6175K–ATARM–30-Aug-10
Analog-to-Digital Converter (ADC)
ADC: DRDY Bit Cleared
ADC: DRDY not Cleared on Disable
ADC: DRDY Possibly Skipped due to CDR Read
ADC: Possible Skip on DRDY when Disabling a Channel
ADC: GOVRE Bit is not Updated
ADC: GOVRE Bit is not Set when Reading CDR
Refer to
Note: AT91SAM7S32 Revision B chip ID is 0x2708 0341.
The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Regis-
ter). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY
flag.
None
When reading LCDR at the same instant as an end of conversion, with DRDY already active,
DRDY is kept active regardless of the enable status of the current channel. This sets DRDY,
whereas new data is not stored.
None
Reading CDR for channel “y” at the same instant as an end of conversion on channel “x” with
EOC[x] already active, leads to skipping to set the DRDY flag if channel “x” is enabled.
Use of DRDY functionality with access to CDR registers should be avoided.
DRDY does not rise when disabling channel “y” at the same time as an end of “x” channel con-
version, although data is stored into CDRx and LCDR.
None.
Read of the Status Register at the same instant as an end of conversion leads to skipping the
update of the GOVRE (general overrun) flag. GOVRE is neither reset nor set.
For example, if reading the status while an end of conversion is occurring and:
None
When reading CDRy (Channel Data Register y) at the same instant as an end of conversion on
channel “x” with the following conditions:
1. GOVRE is active but DRDY is inactive, does not correspond to a new general overrun
2. GOVRE is inactive but DRDY is active, does correspond to a new general overrun con-
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
condition but the GOVRE flag is not reset.
dition but the GOVRE flag is not set.
Section 40.1 “Marking” on page
AT91SAM7S Series Preliminary
591.
737
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