AT91SAM7S512-MU-999 Atmel, AT91SAM7S512-MU-999 Datasheet - Page 425
![IC MCU ARM7 512KB FLASH 64-VQFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT91SAM7S512-MU-999
Manufacturer Part Number
AT91SAM7S512-MU-999
Description
IC MCU ARM7 512KB FLASH 64-VQFN
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S512-MU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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• CKG: Receive Clock Gating Selection
• START: Receive Start Selection
• STOP: Receive Stop Selection
0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
6175K–ATARM–30-Aug-10
0x9-0xF
START
CKG
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
None, continuous clock
Receive Clock enabled only if RF Low
Receive Clock enabled only if RF High
Reserved
Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
Transmit start
Detection of a low level on RF signal
Detection of a high level on RF signal
Detection of a falling edge on RF signal
Detection of a rising edge on RF signal
Detection of any level change on RF signal
Detection of any edge on RF signal
Compare 0
Reserved
Receive Clock Gating
Receive Start
AT91SAM7S Series Preliminary
425
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