AT91SAM7S512-MU-999 Atmel, AT91SAM7S512-MU-999 Datasheet - Page 678
![IC MCU ARM7 512KB FLASH 64-VQFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT91SAM7S512-MU-999
Manufacturer Part Number
AT91SAM7S512-MU-999
Description
IC MCU ARM7 512KB FLASH 64-VQFN
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S512-MU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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40.13.3
40.13.3.1
40.13.3.2
40.13.3.3
40.13.4
40.13.4.1
40.13.5
40.13.5.1
678
AT91SAM7S Series Preliminary
Pulse Width Modulation Controller (PWM)
Real Time Timer (RTT)
USART: Universal Synchronous Asynchronous Receiver Transmitter
PWM: Update when PWM_CCNTx = 0 or 1
PWM: Update when PWM_CPRDx = 0
PWM: Counter Start Value
RTT: Possible Event Loss when Reading RTT_SR
USART: DCD is active High instead of Low
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty
Cycle Register is directly modified when writing the Channel Update Register.
Check the Channel Counter Register before writing the update register.
When Channel Period Register equals 0, the period update is not operational.
Do not write 0 in the period register.
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter
starts at 1.
None.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the
RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event.
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Add an inverter.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
6175K–ATARM–30-Aug-10
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