AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 31

IC MCU FLASH MP3 DECODER 80-TQFP

AT80C51SND1C-ROTIL

Manufacturer Part Number
AT80C51SND1C-ROTIL
Description
IC MCU FLASH MP3 DECODER 80-TQFP
Manufacturer
Atmel
Series
80Cr
Datasheet

Specifications of AT80C51SND1C-ROTIL

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
44
Program Memory Type
ROMless
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
AT80C51SND1CROTIL

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT80C51SND1C-ROTIL
Manufacturer:
Atmel
Quantity:
10 000
7.4
4109L–8051–02/08
Registers
Table 29. PSW Register
PSW (S:8Eh) – Program Status Word Register
Reset Value = 0000 0000b
Table 30. AUXR Register
AUXR (S:8Eh) – Auxiliary Control Register
Number
Number
3 - 2
4 - 3
Bit
CY
Bit
7
6
5
4
7
7
6
5
2
1
0
7
-
Mnemonic Description
Mnemonic Description
DPHDIS
XRS1:0
EXT16
EXT16
RS1:0
M0
AC
CY
AC
OV
Bit
Bit
F0
F1
P
6
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
External 16-bit Access Enable Bit
Set to enable 16-bit access mode during MOVX instructions.
Clear to disable 16-bit access mode and enable standard 8-bit access mode
during MOVX instructions.
External Memory Access Stretch Bit
Set to stretch RD or WR signals duration to 15 CPU clock periods.
Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.
DPH Disable Bit
Set to disable DPH output on P2 when executing MOVX @DPTR instruction.
Clear to enable DPH output on P2 when executing MOVX @DPTR instruction.
Expanded RAM Size Bits
Refer to Table 27 for ERAM size description.
Carry Flag
Carry out from bit 1 of ALU operands.
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
User Definable Flag 0
Register Bank Select Bits
Refer to Table 26 for bits description.
Overflow Flag
Overflow set by arithmetic operations.
User Definable Flag 1
Parity Bit
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
M0
F0
5
5
DPHDIS
RS1
4
4
XRS1
RS0
3
3
AT8xC51SND1C
XRS0
OV
2
2
EXTRAM
F1
1
1
AO
P
0
0
31

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