AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 147

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

19. Synchronous Peripheral Interface
Figure 19-1. Typical Master SPI Bus Configuration
Figure 19-2. Typical Slave SPI Bus Configuration
4109L–8051–02/08
AT8xC51SND1C
MASTER
The AT8xC51SND1C implements a Synchronous Peripheral Interface with master and slave
modes capability.
Figure 19-1 shows an SPI bus configuration using the AT8xC51SND1C as master connected to
slave peripherals while Figure 19-2 shows an SPI bus configuration using the AT8xC51SND1C
as slave of an other master.
The bus is made of three wires connecting all the devices together:
•
•
•
Each slave peripheral is selected by one Slave Select pin (SS). If there is only one slave, it may
be continuously selected with SS tied to a low level. Otherwise, the AT8xC51SND1C may select
each device by software through port pins (Pn.x). Special care should be taken not to select 2
slaves at the same time to avoid bus conflicts.
MISO
MOSI
SCK
SSn
SS1
SS0
P4.0
P4.1
P4.2
Pn.z
Pn.y
Pn.x
Master Output Slave Input (MOSI): it is used to transfer data in series from the master to a
slave.
It is driven by the master.
Master Input Slave Output (MISO): it is used to transfer data in series from a slave to the
master.
It is driven by the selected slave.
Serial Clock (SCK): it is used to synchronize the data transmission both in and out the
devices through their MOSI and MISO lines. It is driven by the master for eight clock cycles
which allows to exchange one Byte on the serial lines.
MISO
MOSI
SCK
SS
SS
SO
SO
DataFlash 1
Slave 1
SI
SI
SCK
SCK
SS
SS
SO
SO
DataFlash 2
Slave 2
SI
SI
SCK
SCK
AT8xC51SND1C
MISO MOSI SCK
SS
AT8xC51SND1C
SS
SO
Slave n
Controller
SI
LCD
SCK
147